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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b76f4d533f2sm1231551266b.0.2025.12.01.05.40.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Dec 2025 05:40:41 -0800 (PST) Message-ID: <509b970e-89bb-4331-a558-8b6fc54b470b@oss.qualcomm.com> Date: Mon, 1 Dec 2025 14:40:39 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: x1e: bus is 40-bits (fix 64GB models) To: Jonathan Marek , Stephan Gerhold Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Abel Vesa , Rajendra Nayak , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list References: <20251127212943.24480-1-jonathan@marek.ca> <1f2c4e5b-2d7d-41cd-9772-374e3de46a50@oss.qualcomm.com> <45bee524-d960-5b24-83bd-4dfb3e78fb1d@marek.ca> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <45bee524-d960-5b24-83bd-4dfb3e78fb1d@marek.ca> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=TcKbdBQh c=1 sm=1 tr=0 ts=692d9adb cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RAbU-raeAAAA:8 a=EUspDBNiAAAA:8 a=SEy8FXNfZs6TXO5W6OgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=ODZdjJIeia2B_SHc_B0f:22 a=JiizpSU_mAIq9zsZDqn2:22 X-Proofpoint-ORIG-GUID: GUnCGpgtpvDWian4ME_8Z8J5d4aEFFse X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjAxMDExMSBTYWx0ZWRfXz+e5E7oNxV/o ChpeO1IlrJlsNduE5IiwLnDIzK0bf7P6X2BqiZ9ueP4++o9VEJoSxzVQcMmLYqsSkAbXEBFD9VR BAElW06ra0w8y3QOwecRoyas2+WTjocd5LW9DrCqRxdNieug/GeNzgkhv9xGWIQ6NzHJttvxIg8 OgXb3i1RWGqe43tf+Vj/HKgUHUJe6VAzZPMIOSUQROsOPvL0pMkxnim5Jf6WwrzsLuYa2XAzCVW bQOkmhd/LDsAYWxBmOzJHYzFYTJT5cH3Tv0Eks6541ZS1LrFgqRGBJWsr9fP5FQSEzsI+uDRBYG 58rniHUJOvnQXMJlBD1gUNQbvKOTzjpIdCsgwRYBT7d4B/gzJE1gzy3B23zqv57iGEUoRy9I13p h6GqY/Zxw4lKzyttDuICscUeYDhQgA== X-Proofpoint-GUID: GUnCGpgtpvDWian4ME_8Z8J5d4aEFFse X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_08,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 malwarescore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512010111 On 11/28/25 3:49 PM, Jonathan Marek wrote: > On 11/28/25 5:52 AM, Konrad Dybcio wrote: >> On 11/28/25 11:26 AM, Stephan Gerhold wrote: >>> On Thu, Nov 27, 2025 at 04:29:42PM -0500, Jonathan Marek wrote: >>>> Unlike the phone SoCs this was copied from, x1e has a 40-bit physical bus. >>>> The upper address space is used to support more than 32GB of memory. >>>> >>>> This fixes issues when DMA buffers are allocated outside the 36-bit range. >>>> >>>> Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") >>>> Signed-off-by: Jonathan Marek >>>> --- >>>>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 4 ++-- >>>>   1 file changed, 2 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>>> index cff34d1c74b60..cd34ce5dfd63a 100644 >>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>>> @@ -792,8 +792,8 @@ soc: soc@0 { >>>>             #address-cells = <2>; >>>>           #size-cells = <2>; >>>> -        dma-ranges = <0 0 0 0 0x10 0>; >>>> -        ranges = <0 0 0 0 0x10 0>; >>>> +        dma-ranges = <0 0 0 0 0x100 0>; >>>> +        ranges = <0 0 0 0 0x100 0>; >>>>   >>> >>> Could you clarify which "issues" (crashes?) you are referring to? >>> >>> We need to distinguish two distinct use cases here, which are both >>> (somewhat) supported upstream: Running in EL1 with the Gunyah hypervisor >>> with the regular DTB and in EL2 with the x1-el2.dtbo applied. >>> >>> # EL2 with x1-el2.dtbo >>> >>> For EL2, I think the 40-bit dma-ranges should indeed work correctly, so >>> we could add your proposed change inside x1-el2.dtso. I'm not sure which >>> issues we are fixing with that though (besides correctness of the >>> hardware description). In EL2, all DMA devices should be behind an >>> IOMMU. In this case, the dma-ranges limit the size of the I/O virtual >>> addresses (DMA addresses) that are given to the devices. The IOMMU maps >>> the DMA buffers to arbitrary physical memory addresses (including >>> outside of the 36-bit range, dma-ranges limits only the DMA address). >> >> I've been carrying something similar in my working tree for quite >> some time too.. The USB4 PCIe controllers have BAR spaces in the >36b >> region, so this will be necessary anyway. >> >> As for the broken-firmware laptops, there's only so much we can do. >> A fix for this has been *long* released, but it's up to the OEMs to >> pull it in. >> >> >> I'm not fully sure, but I think certain subsystems still have the 36b >> address limitation (camera?), so it would be good to know whether that >> needs to be accounted for >> >> Konrad >> > > Most devices only support 32-bit address space, and use a 32-bit DMA mask (which is the default, I think?) to only get 32-bit virtual addresses. Camera driver can set a 36-bit DMA mask if it wants to use its whole range. Right > This patch is about the physical addresses, not virtual. Every device can access the full range (without this, the iommu dma driver thinks buffers with physical addresses outside 36-bit range are not accessible, and tries to use bounce buffers) Yeah this definitely checks out With discussions about some broken firmware devices becoming more obviously broken in mind: Reviewed-by: Konrad Dybcio Konrad