From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christopher Covington Subject: Re: [PATCH] ARM: dts: msm8974: Move arch-timer out of soc node Date: Mon, 17 Mar 2014 13:48:22 -0400 Message-ID: <53273566.20208@codeaurora.org> References: <1394573058-18561-1-git-send-email-sboyd@codeaurora.org> <5327316B.6040007@codeaurora.org> <26E59402-2F50-4E42-AAF2-AF321CB51799@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <26E59402-2F50-4E42-AAF2-AF321CB51799@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: Kumar Gala Cc: Stephen Boyd , David Brown , "linux-kernel@vger.kernel.org" , "linux-arm-msm@vger.kernel.org" , linux-arm-kernel@lists.infradead.org List-Id: linux-arm-msm@vger.kernel.org Hi Kumar, On 03/17/2014 01:33 PM, Kumar Gala wrote: >=20 > On Mar 17, 2014, at 12:31 PM, Christopher Covington wrote: >=20 >> Hi Stephen, >> >> On 03/11/2014 05:24 PM, Stephen Boyd wrote: >>> The architected timer is not a register addressable piece of >>> hardware. Instead it's accessed through cp15 accessors. Move it >>> to the root of the devicetree to reflect this. >> >> I find this confusing, perhaps due to overloading of the word "regis= ter". >> Aren't CP15's a class of coprocessor _registers_? Could it perhaps b= e clearer >> to talk about memory-mapped versus CP15-mapped timers? >> >> Is "soc" documented somewhere or is it just a name for a container? = Assuming >> the latter, it's not obvious to me why being a child of a system on = chip node >> would imply having memory mapped registers. >=20 > =93soc=94 is a container, since its compatible =3D "simple-bus=94, th= is implies > memory mapped register access for nodes inside of it. That makes sense. Thanks for explaining it. Christopher --=20 Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by the Linux Foundation.