From: Stephen Boyd <sboyd@codeaurora.org>
To: Borislav Petkov <bp@alien8.de>
Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org,
Stepan Moskovchenko <stepanm@codeaurora.org>
Subject: Re: [PATCH v6 4/5] edac: Add support for Krait CPU cache error detection
Date: Tue, 08 Apr 2014 12:54:47 -0700 [thread overview]
Message-ID: <53445407.1010108@codeaurora.org> (raw)
In-Reply-To: <20140408173541.GO30077@pd.tnic>
On 04/08/14 10:35, Borislav Petkov wrote:
> On Fri, Apr 04, 2014 at 12:57:29PM -0700, Stephen Boyd wrote:
>> +
>> +struct krait_edac_error {
>> + const char * const msg;
>> + void (*func)(struct edac_device_ctl_info *edac_dev,
>> + int inst_nr, int block_nr, const char *msg);
> arg alignment (please start new line at the opening brace).
Done.
>> + int print_regs = cesr & CESR_PRINT_MASK;
>> + int i;
>> + static const struct krait_edac_error errors[] = {
>> + { "D-cache tag parity error", edac_device_handle_ue },
>> + { "D-cache data parity error", edac_device_handle_ue },
>> + { "I-cache tag parity error", edac_device_handle_ce },
>> + { "I-cache data parity error", edac_device_handle_ce },
>> + { "D-cache tag timing error", edac_device_handle_ue },
>> + { "D-cache data timing error", edac_device_handle_ue },
>> + { "I-cache tag timing error", edac_device_handle_ce },
>> + { "I-cache data timing error", edac_device_handle_ce }
>> + };
>> +
>> + if (print_regs) {
> This variable is used only once here, you can simply do the binary and
> test then and drop it:
>
> if (cesr & CESR_PRINT_MASK)
Done.
>
>> + pr_alert("L1 / TLB Error detected on CPU %d!\n", cpu);
>> + pr_alert("CESR = 0x%08x\n", cesr);
> You can use the edac_*_printk with KERN_ALERT as level which adds proper
> prefixes.
Done.
>
>
>> +
>> + if (cesr & CESR_TLBMH) {
>> + asm ("mcr p15, 0, r0, c8, c7, 0");
>> + edac_device_handle_ce(edac, cpu, 0, "TLB Multi-Hit error");
>> + }
>> +
>> + if (cesr & (CESR_ICTPE | CESR_ICDPE | CESR_ICTE)) {
>> + i_cesynr = read_cesynr();
>> + pr_alert("I-side CESYNR = 0x%08x\n", i_cesynr);
> edac_printk
>
> and also, this message looks a bit cryptic for issuing it at ALERT
> level. I'm ssuming people won't come to you and ask you what it
> means...? :)
Ok. I can lower it to error level?
>
>> + write_cesr(CESR_I_MASK);
>> +
>> + /*
>> + * Clear the I-side bits from the captured CESR value so that we
>> + * don't accidentally clear any new I-side errors when we do
>> + * the CESR write-clear operation.
>> + */
>> + cesr &= ~CESR_I_MASK;
>> + }
>> +
>> + if (cesr & (CESR_DCTPE | CESR_DCDPE | CESR_DCTE)) {
>> + d_cesynr = read_cesynr();
>> + pr_alert("D-side CESYNR = 0x%08x\n", d_cesynr);
> Ditto.
>
>> + }
>> +
>> + /* Clear the interrupt bits we processed */
>> + write_cesr(cesr);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static irqreturn_t krait_l2_irq(int irq, void *dev_id)
>> +{
>> + struct edac_device_ctl_info *edac = dev_id;
>> + unsigned int l2esr;
>> + unsigned int l2esynr0;
>> + unsigned int l2esynr1;
>> + unsigned int l2ear0;
>> + unsigned int l2ear1;
>> + unsigned long cpu;
>> + int i;
>> + static const struct krait_edac_error errors[] = {
>> + { "master port decode error", edac_device_handle_ce },
>> + { "master port slave error", edac_device_handle_ce },
>> + { "tag soft error, single-bit", edac_device_handle_ce },
>> + { "tag soft error, double-bit", edac_device_handle_ue },
>> + { "data soft error, single-bit", edac_device_handle_ce },
>> + { "data soft error, double-bit", edac_device_handle_ue },
>> + { "modified soft error", edac_device_handle_ce },
>> + { "slave port exclusive monitor not available",
>> + edac_device_handle_ue},
>> + { "master port LDREX received Normal OK response",
>> + edac_device_handle_ce },
>> + };
>> +
>> + l2esr = krait_get_l2_indirect_reg(L2ESR);
>> + pr_alert("Error detected!\n");
> Why print this not very telling message here if errors[i].func() will
> get the proper .msg later?
Sure I can drop it.
>
>> + pr_alert("L2ESR = 0x%08x\n", l2esr);
>> +
>> + if (l2esr & (L2ESR_TSESB | L2ESR_TSEDB | L2ESR_MSE | L2ESR_SP)) {
>> + l2esynr0 = krait_get_l2_indirect_reg(L2ESYNR0);
>> + l2esynr1 = krait_get_l2_indirect_reg(L2ESYNR1);
>> + l2ear0 = krait_get_l2_indirect_reg(L2EAR0);
>> + l2ear1 = krait_get_l2_indirect_reg(L2EAR1);
>> +
>> + pr_alert("L2ESYNR0 = 0x%08x\n", l2esynr0);
>> + pr_alert("L2ESYNR1 = 0x%08x\n", l2esynr1);
>> + pr_alert("L2EAR0 = 0x%08x\n", l2ear0);
>> + pr_alert("L2EAR1 = 0x%08x\n", l2ear1);
> Also, please use edac_printk and consider making those messages
> human-readable, otherwise it only confuses users.
Ok.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
next prev parent reply other threads:[~2014-04-08 19:54 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-04 19:57 [PATCH v6 0/5] Krait L1/L2 EDAC driver Stephen Boyd
2014-04-04 19:57 ` [PATCH v6 1/5] genirq: export percpu irq functions for module usage Stephen Boyd
2014-04-04 19:57 ` [PATCH v6 2/5] ARM: Add Krait L2 register accessor functions Stephen Boyd
2014-04-07 20:18 ` Borislav Petkov
2014-04-07 21:56 ` Stephen Boyd
2014-04-08 6:43 ` Borislav Petkov
2014-04-08 14:25 ` Christopher Covington
2014-04-08 15:10 ` Borislav Petkov
2014-04-08 16:19 ` One Thousand Gnomes
2014-04-08 16:42 ` Borislav Petkov
2014-04-04 19:57 ` [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts Stephen Boyd
2014-04-08 15:39 ` Borislav Petkov
2014-04-08 19:55 ` Stephen Boyd
[not found] ` <20140408153925.GJ30077-fF5Pk5pvG8Y@public.gmane.org>
2014-04-29 10:34 ` Lorenzo Pieralisi
2014-04-29 19:02 ` Borislav Petkov
2014-04-04 19:57 ` [PATCH v6 4/5] edac: Add support for Krait CPU cache error detection Stephen Boyd
2014-04-08 17:35 ` Borislav Petkov
2014-04-08 19:54 ` Stephen Boyd [this message]
2014-04-09 15:24 ` Borislav Petkov
2014-04-04 19:57 ` [PATCH v6 5/5] ARM: dts: msm: Fix Krait CPU/L2 nodes Stephen Boyd
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=53445407.1010108@codeaurora.org \
--to=sboyd@codeaurora.org \
--cc=bp@alien8.de \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-edac@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=stepanm@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).