From mboxrd@z Thu Jan 1 00:00:00 1970 From: Srinivas Kandagatla Subject: Re: [PATCH v3 06/13] mmc: mmci: Qcomm: Add 3 clock cycle delay after register write Date: Mon, 26 May 2014 18:04:31 +0100 Message-ID: <5383741F.8010205@linaro.org> References: <1400849362-7007-1-git-send-email-srinivas.kandagatla@linaro.org> <1400849504-7302-1-git-send-email-srinivas.kandagatla@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-mmc-owner@vger.kernel.org To: Ulf Hansson Cc: Russell King , linux-mmc , Chris Ball , "linux-kernel@vger.kernel.org" , linux-arm-msm@vger.kernel.org, Linus Walleij List-Id: linux-arm-msm@vger.kernel.org > > I am not sure I like this approach. For each and every writel > (including pio_writes) you will add a few cpu cycles, since you need > to check for "mclk_delayed_writes" no matter of variant. > > How about, adding a new function pointer in the struct mmci_host, for > "writel operations" which you could set up in probe phase instead? > Yes, this is an additional check for other variants. I will try the function pointer method that you suggested. Thanks, srini > Kind regards > Ulf Hansson >