From mboxrd@z Thu Jan 1 00:00:00 1970 From: Srinivas Kandagatla Subject: Re: [PATCH v3 10/13] mmc: mmci: add Qcom specifics of clk and datactrl registers. Date: Wed, 28 May 2014 10:41:27 +0100 Message-ID: <5385AF47.8030909@linaro.org> References: <1400849362-7007-1-git-send-email-srinivas.kandagatla@linaro.org> <1400849556-7501-1-git-send-email-srinivas.kandagatla@linaro.org> <5383B44F.30608@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: Received: from mail-lb0-f180.google.com ([209.85.217.180]:36188 "EHLO mail-lb0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751936AbaE1Jlc (ORCPT ); Wed, 28 May 2014 05:41:32 -0400 Received: by mail-lb0-f180.google.com with SMTP id p9so5531090lbv.25 for ; Wed, 28 May 2014 02:41:31 -0700 (PDT) In-Reply-To: <5383B44F.30608@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Ulf Hansson Cc: Russell King , linux-mmc , Chris Ball , "linux-kernel@vger.kernel.org" , linux-arm-msm@vger.kernel.org, Linus Walleij Hi Ulf, On 26/05/14 22:38, Srinivas Kandagatla wrote: >>> 2 files changed, 28 insertions(+) >>> >>> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c >>> index 17e7f6a..6434f5b1 100644 >>> --- a/drivers/mmc/host/mmci.c >>> +++ b/drivers/mmc/host/mmci.c >>> @@ -185,6 +185,10 @@ static struct variant_data variant_qcom = { >>> .fifosize = 16 * 4, >>> .fifohalfsize = 8 * 4, >>> .clkreg = MCI_CLK_ENABLE, >>> + .clkreg_enable = MCI_QCOM_CLK_FLOWENA | >>> + MCI_QCOM_CLK_FEEDBACK_CLK, >> >> Obviously I don't have the in-depth knowledge about the Qcom variant, >> but comparing the ST variant here made me think. >> >> Using the feeback clock internal logic in the ST variant, requires the >> corresponding feedback clock pin signal on the board, to be >> routed/connected. Typically we used this for SD cards, which involved >> using an external level shifter circuit. >> >> Is it correct to enable this bit for all cases, including eMMC? >> > You are correct, FBCLK should specific to the board, and I will try to > do something on the same lines as ST variant in next version. I get lot of I/O errors when I remove this flag for test. I rechecked schematics and datasheet, the feedback clk that we refer here is the the feedback clk from CLK pad, there is no separate input pad for fbclk. So I think this is internally feedbacked clk. This selection is configuring bits to latch data and command coming in using feedback clock from CLK pad. I will make sure that the macro is named more appropriately to reflect the same. thanks, srini