[PATCH] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[PATCH] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Srinivas Kandagatla]

Add a PHY driver for uses with AHCI based SATA controller driver on the
APQ8064 family of SoCs.

This patch is a forward port plus separating PHY code of SATA driver
from Qualcomm's v3.4 andriod kernel.

Tested on IFC6410 board.

CC: Sujit Reddy Thumma <sthumma@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 drivers/phy/Kconfig                 |   7 +
 drivers/phy/Makefile                |   1 +
 drivers/phy/phy-qcom-apq8064-sata.c | 358 ++++++++++++++++++++++++++++++++++++
 3 files changed, 366 insertions(+)
 create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index b7b6bce..39083c7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,6 +178,13 @@ config PHY_XGENE
 	help
 	  This option enables support for APM X-Gene SoC multi-purpose PHY.
 
+config PHY_QCOM_APQ8064_SATA
+	tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
+	depends on ARCH_QCOM
+	depends on HAS_IOMEM
+	depends on OF
+	select GENERIC_PHY
+
 config PHY_QCOM_IPQ806X_SATA
 	tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
 	depends on ARCH_QCOM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d950317..8782088 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,4 +20,5 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-apq8064-sata.c b/drivers/phy/phy-qcom-apq8064-sata.c
new file mode 100644
index 0000000..e9e59e2
--- /dev/null
+++ b/drivers/phy/phy-qcom-apq8064-sata.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+
+/* PHY registers */
+#define UNIPHY_PLL_REFCLK_CFG		0x000
+#define UNIPHY_PLL_POSTDIV1_CFG		0x004
+#define UNIPHY_PLL_CHGPUMP_CFG		0x008
+#define UNIPHY_PLL_VCOLPF_CFG		0x00C
+#define UNIPHY_PLL_VREG_CFG		0x010
+#define UNIPHY_PLL_PWRGEN_CFG		0x014
+#define UNIPHY_PLL_DMUX_CFG		0x018
+#define UNIPHY_PLL_AMUX_CFG		0x01C
+#define UNIPHY_PLL_GLB_CFG		0x020
+#define UNIPHY_PLL_POSTDIV2_CFG		0x024
+#define UNIPHY_PLL_POSTDIV3_CFG		0x028
+#define UNIPHY_PLL_LPFR_CFG		0x02C
+#define UNIPHY_PLL_LPFC1_CFG		0x030
+#define UNIPHY_PLL_LPFC2_CFG		0x034
+#define UNIPHY_PLL_SDM_CFG0		0x038
+#define UNIPHY_PLL_SDM_CFG1		0x03C
+#define UNIPHY_PLL_SDM_CFG2		0x040
+#define UNIPHY_PLL_SDM_CFG3		0x044
+#define UNIPHY_PLL_SDM_CFG4		0x048
+#define UNIPHY_PLL_SSC_CFG0		0x04C
+#define UNIPHY_PLL_SSC_CFG1		0x050
+#define UNIPHY_PLL_SSC_CFG2		0x054
+#define UNIPHY_PLL_SSC_CFG3		0x058
+#define UNIPHY_PLL_LKDET_CFG0		0x05C
+#define UNIPHY_PLL_LKDET_CFG1		0x060
+#define UNIPHY_PLL_LKDET_CFG2		0x064
+#define UNIPHY_PLL_TEST_CFG		0x068
+#define UNIPHY_PLL_CAL_CFG0		0x06C
+#define UNIPHY_PLL_CAL_CFG1		0x070
+#define UNIPHY_PLL_CAL_CFG2		0x074
+#define UNIPHY_PLL_CAL_CFG3		0x078
+#define UNIPHY_PLL_CAL_CFG4		0x07C
+#define UNIPHY_PLL_CAL_CFG5		0x080
+#define UNIPHY_PLL_CAL_CFG6		0x084
+#define UNIPHY_PLL_CAL_CFG7		0x088
+#define UNIPHY_PLL_CAL_CFG8		0x08C
+#define UNIPHY_PLL_CAL_CFG9		0x090
+#define UNIPHY_PLL_CAL_CFG10		0x094
+#define UNIPHY_PLL_CAL_CFG11		0x098
+#define UNIPHY_PLL_EFUSE_CFG		0x09C
+#define UNIPHY_PLL_DEBUG_BUS_SEL	0x0A0
+#define UNIPHY_PLL_CTRL_42		0x0A4
+#define UNIPHY_PLL_CTRL_43		0x0A8
+#define UNIPHY_PLL_CTRL_44		0x0AC
+#define UNIPHY_PLL_CTRL_45		0x0B0
+#define UNIPHY_PLL_CTRL_46		0x0B4
+#define UNIPHY_PLL_CTRL_47		0x0B8
+#define UNIPHY_PLL_CTRL_48		0x0BC
+#define UNIPHY_PLL_STATUS		0x0C0
+#define UNIPHY_PLL_DEBUG_BUS0		0x0C4
+#define UNIPHY_PLL_DEBUG_BUS1		0x0C8
+#define UNIPHY_PLL_DEBUG_BUS2		0x0CC
+#define UNIPHY_PLL_DEBUG_BUS3		0x0D0
+#define UNIPHY_PLL_CTRL_54		0x0D4
+
+#define SATA_PHY_SER_CTRL		0x100
+#define SATA_PHY_TX_DRIV_CTRL0		0x104
+#define SATA_PHY_TX_DRIV_CTRL1		0x108
+#define SATA_PHY_TX_DRIV_CTRL2		0x10C
+#define SATA_PHY_TX_DRIV_CTRL3		0x110
+#define SATA_PHY_TX_IMCAL0		0x11C
+#define SATA_PHY_TX_IMCAL1		0x120
+#define SATA_PHY_TX_IMCAL2		0x124
+#define SATA_PHY_RX_IMCAL0		0x128
+#define SATA_PHY_RX_IMCAL1		0x12C
+#define SATA_PHY_RX_IMCAL2		0x130
+#define SATA_PHY_RX_TERM		0x134
+#define SATA_PHY_EQUAL			0x13C
+#define SATA_PHY_OOB_TERM		0x144
+#define SATA_PHY_CDR_CTRL0		0x148
+#define SATA_PHY_CDR_CTRL1		0x14C
+#define SATA_PHY_CDR_CTRL2		0x150
+#define SATA_PHY_CDR_CTRL3		0x154
+#define SATA_PHY_CDR_CTRL4		0x158
+#define SATA_PHY_FA_LOAD0		0x15C
+#define SATA_PHY_FA_LOAD1		0x160
+#define SATA_PHY_PI_CTRL0		0x168
+#define SATA_PHY_PI_CTRL1		0x16C
+#define SATA_PHY_AD_TPA_CTRL		0x178
+#define SATA_PHY_REFCLK_CTRL		0x17C
+#define SATA_PHY_POW_DWN_CTRL0		0x180
+#define SATA_PHY_POW_DWN_CTRL1		0x184
+#define SATA_PHY_TX_DATA_CTRL		0x188
+#define SATA_PHY_BIST_GEN0		0x18C
+#define SATA_PHY_BIST_GEN1		0x190
+#define SATA_PHY_BIST_GEN2		0x194
+#define SATA_PHY_BIST_GEN3		0x198
+#define SATA_PHY_LBK_CTRL		0x19C
+#define SATA_PHY_TEST_DEBUG_CTRL	0x1A0
+#define SATA_PHY_ALIGNP			0x1A4
+#define SATA_PHY_PRBS_CFG0		0x1A8
+#define SATA_PHY_PRBS_CFG1		0x1AC
+#define SATA_PHY_PRBS_CFG2		0x1B0
+#define SATA_PHY_PRBS_CFG3		0x1B4
+#define SATA_PHY_CHAN_COMP_CHK_CNT	0x1B8
+#define SATA_PHY_RESET_CTRL		0x1BC
+#define SATA_PHY_RX_CLR			0x1C0
+#define SATA_PHY_RX_EBUF_CTRL		0x1C4
+#define SATA_PHY_ID0			0x1C8
+#define SATA_PHY_ID1			0x1CC
+#define SATA_PHY_ID2			0x1D0
+#define SATA_PHY_ID3			0x1D4
+#define SATA_PHY_RX_CHK_ERR_CNT0	0x1D8
+#define SATA_PHY_RX_CHK_ERR_CNT1	0x1DC
+#define SATA_PHY_RX_CHK_STAT		0x1E0
+#define SATA_PHY_TX_IMCAL_STAT		0x1E4
+#define SATA_PHY_RX_IMCAL_STAT		0x1E8
+#define SATA_PHY_RX_EBUF_STAT		0x1EC
+#define SATA_PHY_DEBUG_BUS_STAT0	0x1F0
+#define SATA_PHY_DEBUG_BUS_STAT1	0x1F4
+#define SATA_PHY_DEBUG_BUS_STAT2	0x1F8
+#define SATA_PHY_DEBUG_BUS_STAT3	0x1FC
+
+#define UNIPHY_PLL_LOCK		BIT(0)
+#define SATA_PHY_TX_CAL		BIT(0)
+#define SATA_PHY_RX_CAL		BIT(0)
+
+/* default timeout set to 1 sec */
+#define TIMEOUT_MS		10000
+
+struct qcom_apq8064_sata_phy {
+	void __iomem *mmio;
+	struct clk *cfg_clk;
+	struct device *dev;
+};
+
+/* Helper function to do poll and timeout */
+static int read_poll_timeout(void __iomem *addr, u32 mask)
+{
+	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
+	u32 val;
+
+	do {
+		cpu_relax();
+		val = readl_relaxed(addr);
+		if (val & mask)
+			break;
+	} while (!time_after(jiffies, timeout));
+
+	return (val & mask) ? 0 : -ETIMEDOUT;
+}
+
+static int qcom_apq8064_sata_phy_init(struct phy *generic_phy)
+{
+	struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
+	void __iomem *base = phy->mmio;
+	int ret = 0;
+
+	/* SATA phy initialization */
+	writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
+	writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
+	/* Make sure the power down happens before power up */
+	mb();
+	usleep_range(10, 60);
+
+	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
+	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
+	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
+	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
+	writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
+
+	/* Write UNIPHYPLL registers to configure PLL */
+	writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
+	writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG);
+
+	writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0);
+	writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8);
+	writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9);
+	writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10);
+	writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11);
+
+	writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0);
+	writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1);
+	writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2);
+	writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3);
+	writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4);
+
+	writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0);
+	writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1);
+	writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2);
+	writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3);
+
+	writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0);
+	writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1);
+
+	writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG);
+	/* make sure global config LDO power down happens before power up */
+	mb();
+
+	writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG);
+	writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2);
+
+	/* PLL Lock wait */
+	ret = read_poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK);
+	if (ret) {
+		dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n");
+		return ret;
+	}
+
+	/* TX Calibration */
+	ret = read_poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL);
+	if (ret) {
+		dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n");
+		return ret;
+	}
+
+	/* RX Calibration */
+	ret = read_poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL);
+	if (ret) {
+		dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n");
+		return ret;
+	}
+
+	/* SATA phy calibrated succesfully, power up to functional mode */
+	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
+	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
+	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
+
+	writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1);
+	writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0);
+	writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1);
+	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2);
+	writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0);
+	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3);
+	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
+
+	writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL);
+	writel_relaxed(0x43, base + SATA_PHY_ALIGNP);
+	writel_relaxed(0x04, base + SATA_PHY_OOB_TERM);
+
+	writel_relaxed(0x01, base + SATA_PHY_EQUAL);
+	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0);
+	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1);
+
+	return 0;
+}
+
+static int qcom_apq8064_sata_phy_exit(struct phy *generic_phy)
+{
+	struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
+	void __iomem *base = phy->mmio;
+
+	/* Power down PHY */
+	writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0);
+	writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1);
+
+	/* Power down PLL block */
+	writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG);
+
+	return 0;
+}
+
+static struct phy_ops qcom_apq8064_sata_phy_ops = {
+	.init		= qcom_apq8064_sata_phy_init,
+	.exit		= qcom_apq8064_sata_phy_exit,
+	.owner		= THIS_MODULE,
+};
+
+static int qcom_apq8064_sata_phy_probe(struct platform_device *pdev)
+{
+	struct qcom_apq8064_sata_phy *phy;
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct phy_provider *phy_provider;
+	struct phy *generic_phy;
+	int ret;
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	phy->mmio = devm_ioremap_resource(dev, res);
+	if (IS_ERR(phy->mmio))
+		return PTR_ERR(phy->mmio);
+
+	generic_phy = devm_phy_create(dev, &qcom_apq8064_sata_phy_ops, NULL);
+	if (IS_ERR(generic_phy)) {
+		dev_err(dev, "%s: failed to create phy\n", __func__);
+		return PTR_ERR(generic_phy);
+	}
+
+	phy->dev = dev;
+	phy_set_drvdata(generic_phy, phy);
+
+	phy->cfg_clk = devm_clk_get(dev, "cfg");
+	if (IS_ERR(phy->cfg_clk)) {
+		dev_err(dev, "Failed to get sata cfg clock\n");
+		return PTR_ERR(phy->cfg_clk);
+	}
+
+	ret = clk_prepare_enable(phy->cfg_clk);
+	if (ret)
+		return ret;
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(phy_provider)) {
+		clk_disable_unprepare(phy->cfg_clk);
+		dev_err(dev, "%s: failed to register phy\n", __func__);
+		return PTR_ERR(phy_provider);
+	}
+
+	return 0;
+}
+
+static int qcom_apq8064_sata_phy_remove(struct platform_device *pdev)
+{
+	struct qcom_apq8064_sata_phy *phy = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(phy->cfg_clk);
+
+	return 0;
+}
+
+static const struct of_device_id qcom_apq8064_sata_phy_of_match[] = {
+	{ .compatible = "qcom,apq8064-sata-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, qcom_apq8064_sata_phy_of_match);
+
+static struct platform_driver qcom_apq8064_sata_phy_driver = {
+	.probe	= qcom_apq8064_sata_phy_probe,
+	.remove	= qcom_apq8064_sata_phy_remove,
+	.driver = {
+		.name	= "qcom-apq8064-sata-phy",
+		.owner	= THIS_MODULE,
+		.of_match_table	= qcom_apq8064_sata_phy_of_match,
+	}
+};
+module_platform_driver(qcom_apq8064_sata_phy_driver);
+
+MODULE_DESCRIPTION("QCOM apq8064 SATA PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

Re: [PATCH] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Kumar Gala]

On Jun 23, 2014, at 1:00 PM, Srinivas Kandagatla <srinivas.kandagatla@linaro.org> wrote:

> Add a PHY driver for uses with AHCI based SATA controller driver on the
> APQ8064 family of SoCs.
> 
> This patch is a forward port plus separating PHY code of SATA driver
> from Qualcomm's v3.4 andriod kernel.
> 
> Tested on IFC6410 board.
> 
> CC: Sujit Reddy Thumma <sthumma@codeaurora.org>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> ---
> drivers/phy/Kconfig                 |   7 +
> drivers/phy/Makefile                |   1 +
> drivers/phy/phy-qcom-apq8064-sata.c | 358 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 366 insertions(+)
> create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c

Did you look at the 3.10 Android kernel tree version of the phy driver?

Also do you have a DT binding spec to go with this?

- k

Re: [PATCH] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Srinivas Kandagatla]

On 23/06/14 19:12, Kumar Gala wrote:
>
> On Jun 23, 2014, at 1:00 PM, Srinivas Kandagatla <srinivas.kandagatla@linaro.org> wrote:
>
>> Add a PHY driver for uses with AHCI based SATA controller driver on the
>> APQ8064 family of SoCs.
>>
>> This patch is a forward port plus separating PHY code of SATA driver
>> from Qualcomm's v3.4 andriod kernel.
>>
>> Tested on IFC6410 board.
>>
>> CC: Sujit Reddy Thumma <sthumma@codeaurora.org>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
>> ---
>> drivers/phy/Kconfig                 |   7 +
>> drivers/phy/Makefile                |   1 +
>> drivers/phy/phy-qcom-apq8064-sata.c | 358 ++++++++++++++++++++++++++++++++++++
>> 3 files changed, 366 insertions(+)
>> create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c
>
> Did you look at the 3.10 Android kernel tree version of the phy driver?
>
No, I did not get a chance to look at it. I will have a look at it today.
> Also do you have a DT binding spec to go with this?
yes, I did add it into the same binding spec qcom-phy.txt as ipq806x.

I will send this in a different patch.

thanks,
srini
>
> - k
>

Re: [PATCH] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Srinivas Kandagatla]

Hi Kishon,

Could you please consider this for v3.17?


Thanks,
srini

On 23/06/14 19:00, Srinivas Kandagatla wrote:
> Add a PHY driver for uses with AHCI based SATA controller driver on the
> APQ8064 family of SoCs.
>
> This patch is a forward port plus separating PHY code of SATA driver
> from Qualcomm's v3.4 andriod kernel.
>
> Tested on IFC6410 board.
>
> CC: Sujit Reddy Thumma <sthumma@codeaurora.org>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> ---
>   drivers/phy/Kconfig                 |   7 +
>   drivers/phy/Makefile                |   1 +
>   drivers/phy/phy-qcom-apq8064-sata.c | 358 ++++++++++++++++++++++++++++++++++++
>   3 files changed, 366 insertions(+)
>   create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index b7b6bce..39083c7 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -178,6 +178,13 @@ config PHY_XGENE
>   	help
>   	  This option enables support for APM X-Gene SoC multi-purpose PHY.
>
> +config PHY_QCOM_APQ8064_SATA
> +	tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
> +	depends on ARCH_QCOM
> +	depends on HAS_IOMEM
> +	depends on OF
> +	select GENERIC_PHY
> +
>   config PHY_QCOM_IPQ806X_SATA
>   	tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
>   	depends on ARCH_QCOM
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index d950317..8782088 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -20,4 +20,5 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o
>   phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>   obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o
> +obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>   obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
> diff --git a/drivers/phy/phy-qcom-apq8064-sata.c b/drivers/phy/phy-qcom-apq8064-sata.c
> new file mode 100644
> index 0000000..e9e59e2
> --- /dev/null
> +++ b/drivers/phy/phy-qcom-apq8064-sata.c
> @@ -0,0 +1,358 @@
> +/*
> + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/time.h>
> +#include <linux/delay.h>
> +#include <linux/clk.h>
> +#include <linux/slab.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +
> +/* PHY registers */
> +#define UNIPHY_PLL_REFCLK_CFG		0x000
> +#define UNIPHY_PLL_POSTDIV1_CFG		0x004
> +#define UNIPHY_PLL_CHGPUMP_CFG		0x008
> +#define UNIPHY_PLL_VCOLPF_CFG		0x00C
> +#define UNIPHY_PLL_VREG_CFG		0x010
> +#define UNIPHY_PLL_PWRGEN_CFG		0x014
> +#define UNIPHY_PLL_DMUX_CFG		0x018
> +#define UNIPHY_PLL_AMUX_CFG		0x01C
> +#define UNIPHY_PLL_GLB_CFG		0x020
> +#define UNIPHY_PLL_POSTDIV2_CFG		0x024
> +#define UNIPHY_PLL_POSTDIV3_CFG		0x028
> +#define UNIPHY_PLL_LPFR_CFG		0x02C
> +#define UNIPHY_PLL_LPFC1_CFG		0x030
> +#define UNIPHY_PLL_LPFC2_CFG		0x034
> +#define UNIPHY_PLL_SDM_CFG0		0x038
> +#define UNIPHY_PLL_SDM_CFG1		0x03C
> +#define UNIPHY_PLL_SDM_CFG2		0x040
> +#define UNIPHY_PLL_SDM_CFG3		0x044
> +#define UNIPHY_PLL_SDM_CFG4		0x048
> +#define UNIPHY_PLL_SSC_CFG0		0x04C
> +#define UNIPHY_PLL_SSC_CFG1		0x050
> +#define UNIPHY_PLL_SSC_CFG2		0x054
> +#define UNIPHY_PLL_SSC_CFG3		0x058
> +#define UNIPHY_PLL_LKDET_CFG0		0x05C
> +#define UNIPHY_PLL_LKDET_CFG1		0x060
> +#define UNIPHY_PLL_LKDET_CFG2		0x064
> +#define UNIPHY_PLL_TEST_CFG		0x068
> +#define UNIPHY_PLL_CAL_CFG0		0x06C
> +#define UNIPHY_PLL_CAL_CFG1		0x070
> +#define UNIPHY_PLL_CAL_CFG2		0x074
> +#define UNIPHY_PLL_CAL_CFG3		0x078
> +#define UNIPHY_PLL_CAL_CFG4		0x07C
> +#define UNIPHY_PLL_CAL_CFG5		0x080
> +#define UNIPHY_PLL_CAL_CFG6		0x084
> +#define UNIPHY_PLL_CAL_CFG7		0x088
> +#define UNIPHY_PLL_CAL_CFG8		0x08C
> +#define UNIPHY_PLL_CAL_CFG9		0x090
> +#define UNIPHY_PLL_CAL_CFG10		0x094
> +#define UNIPHY_PLL_CAL_CFG11		0x098
> +#define UNIPHY_PLL_EFUSE_CFG		0x09C
> +#define UNIPHY_PLL_DEBUG_BUS_SEL	0x0A0
> +#define UNIPHY_PLL_CTRL_42		0x0A4
> +#define UNIPHY_PLL_CTRL_43		0x0A8
> +#define UNIPHY_PLL_CTRL_44		0x0AC
> +#define UNIPHY_PLL_CTRL_45		0x0B0
> +#define UNIPHY_PLL_CTRL_46		0x0B4
> +#define UNIPHY_PLL_CTRL_47		0x0B8
> +#define UNIPHY_PLL_CTRL_48		0x0BC
> +#define UNIPHY_PLL_STATUS		0x0C0
> +#define UNIPHY_PLL_DEBUG_BUS0		0x0C4
> +#define UNIPHY_PLL_DEBUG_BUS1		0x0C8
> +#define UNIPHY_PLL_DEBUG_BUS2		0x0CC
> +#define UNIPHY_PLL_DEBUG_BUS3		0x0D0
> +#define UNIPHY_PLL_CTRL_54		0x0D4
> +
> +#define SATA_PHY_SER_CTRL		0x100
> +#define SATA_PHY_TX_DRIV_CTRL0		0x104
> +#define SATA_PHY_TX_DRIV_CTRL1		0x108
> +#define SATA_PHY_TX_DRIV_CTRL2		0x10C
> +#define SATA_PHY_TX_DRIV_CTRL3		0x110
> +#define SATA_PHY_TX_IMCAL0		0x11C
> +#define SATA_PHY_TX_IMCAL1		0x120
> +#define SATA_PHY_TX_IMCAL2		0x124
> +#define SATA_PHY_RX_IMCAL0		0x128
> +#define SATA_PHY_RX_IMCAL1		0x12C
> +#define SATA_PHY_RX_IMCAL2		0x130
> +#define SATA_PHY_RX_TERM		0x134
> +#define SATA_PHY_EQUAL			0x13C
> +#define SATA_PHY_OOB_TERM		0x144
> +#define SATA_PHY_CDR_CTRL0		0x148
> +#define SATA_PHY_CDR_CTRL1		0x14C
> +#define SATA_PHY_CDR_CTRL2		0x150
> +#define SATA_PHY_CDR_CTRL3		0x154
> +#define SATA_PHY_CDR_CTRL4		0x158
> +#define SATA_PHY_FA_LOAD0		0x15C
> +#define SATA_PHY_FA_LOAD1		0x160
> +#define SATA_PHY_PI_CTRL0		0x168
> +#define SATA_PHY_PI_CTRL1		0x16C
> +#define SATA_PHY_AD_TPA_CTRL		0x178
> +#define SATA_PHY_REFCLK_CTRL		0x17C
> +#define SATA_PHY_POW_DWN_CTRL0		0x180
> +#define SATA_PHY_POW_DWN_CTRL1		0x184
> +#define SATA_PHY_TX_DATA_CTRL		0x188
> +#define SATA_PHY_BIST_GEN0		0x18C
> +#define SATA_PHY_BIST_GEN1		0x190
> +#define SATA_PHY_BIST_GEN2		0x194
> +#define SATA_PHY_BIST_GEN3		0x198
> +#define SATA_PHY_LBK_CTRL		0x19C
> +#define SATA_PHY_TEST_DEBUG_CTRL	0x1A0
> +#define SATA_PHY_ALIGNP			0x1A4
> +#define SATA_PHY_PRBS_CFG0		0x1A8
> +#define SATA_PHY_PRBS_CFG1		0x1AC
> +#define SATA_PHY_PRBS_CFG2		0x1B0
> +#define SATA_PHY_PRBS_CFG3		0x1B4
> +#define SATA_PHY_CHAN_COMP_CHK_CNT	0x1B8
> +#define SATA_PHY_RESET_CTRL		0x1BC
> +#define SATA_PHY_RX_CLR			0x1C0
> +#define SATA_PHY_RX_EBUF_CTRL		0x1C4
> +#define SATA_PHY_ID0			0x1C8
> +#define SATA_PHY_ID1			0x1CC
> +#define SATA_PHY_ID2			0x1D0
> +#define SATA_PHY_ID3			0x1D4
> +#define SATA_PHY_RX_CHK_ERR_CNT0	0x1D8
> +#define SATA_PHY_RX_CHK_ERR_CNT1	0x1DC
> +#define SATA_PHY_RX_CHK_STAT		0x1E0
> +#define SATA_PHY_TX_IMCAL_STAT		0x1E4
> +#define SATA_PHY_RX_IMCAL_STAT		0x1E8
> +#define SATA_PHY_RX_EBUF_STAT		0x1EC
> +#define SATA_PHY_DEBUG_BUS_STAT0	0x1F0
> +#define SATA_PHY_DEBUG_BUS_STAT1	0x1F4
> +#define SATA_PHY_DEBUG_BUS_STAT2	0x1F8
> +#define SATA_PHY_DEBUG_BUS_STAT3	0x1FC
> +
> +#define UNIPHY_PLL_LOCK		BIT(0)
> +#define SATA_PHY_TX_CAL		BIT(0)
> +#define SATA_PHY_RX_CAL		BIT(0)
> +
> +/* default timeout set to 1 sec */
> +#define TIMEOUT_MS		10000
> +
> +struct qcom_apq8064_sata_phy {
> +	void __iomem *mmio;
> +	struct clk *cfg_clk;
> +	struct device *dev;
> +};
> +
> +/* Helper function to do poll and timeout */
> +static int read_poll_timeout(void __iomem *addr, u32 mask)
> +{
> +	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
> +	u32 val;
> +
> +	do {
> +		cpu_relax();
> +		val = readl_relaxed(addr);
> +		if (val & mask)
> +			break;
> +	} while (!time_after(jiffies, timeout));
> +
> +	return (val & mask) ? 0 : -ETIMEDOUT;
> +}
> +
> +static int qcom_apq8064_sata_phy_init(struct phy *generic_phy)
> +{
> +	struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
> +	void __iomem *base = phy->mmio;
> +	int ret = 0;
> +
> +	/* SATA phy initialization */
> +	writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
> +	writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
> +	/* Make sure the power down happens before power up */
> +	mb();
> +	usleep_range(10, 60);
> +
> +	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
> +	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
> +	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
> +	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
> +	writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
> +
> +	/* Write UNIPHYPLL registers to configure PLL */
> +	writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
> +	writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG);
> +
> +	writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0);
> +	writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8);
> +	writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9);
> +	writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10);
> +	writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11);
> +
> +	writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0);
> +	writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1);
> +	writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2);
> +	writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3);
> +	writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4);
> +
> +	writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0);
> +	writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1);
> +	writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2);
> +	writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3);
> +
> +	writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0);
> +	writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1);
> +
> +	writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG);
> +	/* make sure global config LDO power down happens before power up */
> +	mb();
> +
> +	writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG);
> +	writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2);
> +
> +	/* PLL Lock wait */
> +	ret = read_poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK);
> +	if (ret) {
> +		dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n");
> +		return ret;
> +	}
> +
> +	/* TX Calibration */
> +	ret = read_poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL);
> +	if (ret) {
> +		dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n");
> +		return ret;
> +	}
> +
> +	/* RX Calibration */
> +	ret = read_poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL);
> +	if (ret) {
> +		dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n");
> +		return ret;
> +	}
> +
> +	/* SATA phy calibrated succesfully, power up to functional mode */
> +	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
> +	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
> +	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
> +
> +	writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1);
> +	writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0);
> +	writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1);
> +	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2);
> +	writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0);
> +	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3);
> +	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
> +
> +	writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL);
> +	writel_relaxed(0x43, base + SATA_PHY_ALIGNP);
> +	writel_relaxed(0x04, base + SATA_PHY_OOB_TERM);
> +
> +	writel_relaxed(0x01, base + SATA_PHY_EQUAL);
> +	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0);
> +	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1);
> +
> +	return 0;
> +}
> +
> +static int qcom_apq8064_sata_phy_exit(struct phy *generic_phy)
> +{
> +	struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
> +	void __iomem *base = phy->mmio;
> +
> +	/* Power down PHY */
> +	writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0);
> +	writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1);
> +
> +	/* Power down PLL block */
> +	writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG);
> +
> +	return 0;
> +}
> +
> +static struct phy_ops qcom_apq8064_sata_phy_ops = {
> +	.init		= qcom_apq8064_sata_phy_init,
> +	.exit		= qcom_apq8064_sata_phy_exit,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int qcom_apq8064_sata_phy_probe(struct platform_device *pdev)
> +{
> +	struct qcom_apq8064_sata_phy *phy;
> +	struct device *dev = &pdev->dev;
> +	struct resource *res;
> +	struct phy_provider *phy_provider;
> +	struct phy *generic_phy;
> +	int ret;
> +
> +	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
> +	if (!phy)
> +		return -ENOMEM;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	phy->mmio = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(phy->mmio))
> +		return PTR_ERR(phy->mmio);
> +
> +	generic_phy = devm_phy_create(dev, &qcom_apq8064_sata_phy_ops, NULL);
> +	if (IS_ERR(generic_phy)) {
> +		dev_err(dev, "%s: failed to create phy\n", __func__);
> +		return PTR_ERR(generic_phy);
> +	}
> +
> +	phy->dev = dev;
> +	phy_set_drvdata(generic_phy, phy);
> +
> +	phy->cfg_clk = devm_clk_get(dev, "cfg");
> +	if (IS_ERR(phy->cfg_clk)) {
> +		dev_err(dev, "Failed to get sata cfg clock\n");
> +		return PTR_ERR(phy->cfg_clk);
> +	}
> +
> +	ret = clk_prepare_enable(phy->cfg_clk);
> +	if (ret)
> +		return ret;
> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider)) {
> +		clk_disable_unprepare(phy->cfg_clk);
> +		dev_err(dev, "%s: failed to register phy\n", __func__);
> +		return PTR_ERR(phy_provider);
> +	}
> +
> +	return 0;
> +}
> +
> +static int qcom_apq8064_sata_phy_remove(struct platform_device *pdev)
> +{
> +	struct qcom_apq8064_sata_phy *phy = platform_get_drvdata(pdev);
> +
> +	clk_disable_unprepare(phy->cfg_clk);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id qcom_apq8064_sata_phy_of_match[] = {
> +	{ .compatible = "qcom,apq8064-sata-phy" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, qcom_apq8064_sata_phy_of_match);
> +
> +static struct platform_driver qcom_apq8064_sata_phy_driver = {
> +	.probe	= qcom_apq8064_sata_phy_probe,
> +	.remove	= qcom_apq8064_sata_phy_remove,
> +	.driver = {
> +		.name	= "qcom-apq8064-sata-phy",
> +		.owner	= THIS_MODULE,
> +		.of_match_table	= qcom_apq8064_sata_phy_of_match,
> +	}
> +};
> +module_platform_driver(qcom_apq8064_sata_phy_driver);
> +
> +MODULE_DESCRIPTION("QCOM apq8064 SATA PHY driver");
> +MODULE_LICENSE("GPL v2");
>

Re: [PATCH] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Kishon Vijay Abraham I]

On Wednesday 09 July 2014 03:06 PM, Srinivas Kandagatla wrote:
> Hi Kishon,
> 
> Could you please consider this for v3.17?
> 

sure.. please send the dt binding docs along with this patch.

Cheers
Kishon
> 
> Thanks,
> srini
> 
> On 23/06/14 19:00, Srinivas Kandagatla wrote:
>> Add a PHY driver for uses with AHCI based SATA controller driver on the
>> APQ8064 family of SoCs.
>>
>> This patch is a forward port plus separating PHY code of SATA driver
>> from Qualcomm's v3.4 andriod kernel.
>>
>> Tested on IFC6410 board.
>>
>> CC: Sujit Reddy Thumma <sthumma@codeaurora.org>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
>> ---
>>   drivers/phy/Kconfig                 |   7 +
>>   drivers/phy/Makefile                |   1 +
>>   drivers/phy/phy-qcom-apq8064-sata.c | 358 ++++++++++++++++++++++++++++++++++++
>>   3 files changed, 366 insertions(+)
>>   create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index b7b6bce..39083c7 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -178,6 +178,13 @@ config PHY_XGENE
>>       help
>>         This option enables support for APM X-Gene SoC multi-purpose PHY.
>>
>> +config PHY_QCOM_APQ8064_SATA
>> +    tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
>> +    depends on ARCH_QCOM
>> +    depends on HAS_IOMEM
>> +    depends on OF
>> +    select GENERIC_PHY
>> +
>>   config PHY_QCOM_IPQ806X_SATA
>>       tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
>>       depends on ARCH_QCOM
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index d950317..8782088 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -20,4 +20,5 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)    +=
>> phy-exynos4x12-usb2.o
>>   phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)    += phy-exynos5250-usb2.o
>>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)    += phy-exynos5-usbdrd.o
>>   obj-$(CONFIG_PHY_XGENE)            += phy-xgene.o
>> +obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)    += phy-qcom-apq8064-sata.o
>>   obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)    += phy-qcom-ipq806x-sata.o
>> diff --git a/drivers/phy/phy-qcom-apq8064-sata.c
>> b/drivers/phy/phy-qcom-apq8064-sata.c
>> new file mode 100644
>> index 0000000..e9e59e2
>> --- /dev/null
>> +++ b/drivers/phy/phy-qcom-apq8064-sata.c
>> @@ -0,0 +1,358 @@
>> +/*
>> + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/time.h>
>> +#include <linux/delay.h>
>> +#include <linux/clk.h>
>> +#include <linux/slab.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/phy/phy.h>
>> +
>> +/* PHY registers */
>> +#define UNIPHY_PLL_REFCLK_CFG        0x000
>> +#define UNIPHY_PLL_POSTDIV1_CFG        0x004
>> +#define UNIPHY_PLL_CHGPUMP_CFG        0x008
>> +#define UNIPHY_PLL_VCOLPF_CFG        0x00C
>> +#define UNIPHY_PLL_VREG_CFG        0x010
>> +#define UNIPHY_PLL_PWRGEN_CFG        0x014
>> +#define UNIPHY_PLL_DMUX_CFG        0x018
>> +#define UNIPHY_PLL_AMUX_CFG        0x01C
>> +#define UNIPHY_PLL_GLB_CFG        0x020
>> +#define UNIPHY_PLL_POSTDIV2_CFG        0x024
>> +#define UNIPHY_PLL_POSTDIV3_CFG        0x028
>> +#define UNIPHY_PLL_LPFR_CFG        0x02C
>> +#define UNIPHY_PLL_LPFC1_CFG        0x030
>> +#define UNIPHY_PLL_LPFC2_CFG        0x034
>> +#define UNIPHY_PLL_SDM_CFG0        0x038
>> +#define UNIPHY_PLL_SDM_CFG1        0x03C
>> +#define UNIPHY_PLL_SDM_CFG2        0x040
>> +#define UNIPHY_PLL_SDM_CFG3        0x044
>> +#define UNIPHY_PLL_SDM_CFG4        0x048
>> +#define UNIPHY_PLL_SSC_CFG0        0x04C
>> +#define UNIPHY_PLL_SSC_CFG1        0x050
>> +#define UNIPHY_PLL_SSC_CFG2        0x054
>> +#define UNIPHY_PLL_SSC_CFG3        0x058
>> +#define UNIPHY_PLL_LKDET_CFG0        0x05C
>> +#define UNIPHY_PLL_LKDET_CFG1        0x060
>> +#define UNIPHY_PLL_LKDET_CFG2        0x064
>> +#define UNIPHY_PLL_TEST_CFG        0x068
>> +#define UNIPHY_PLL_CAL_CFG0        0x06C
>> +#define UNIPHY_PLL_CAL_CFG1        0x070
>> +#define UNIPHY_PLL_CAL_CFG2        0x074
>> +#define UNIPHY_PLL_CAL_CFG3        0x078
>> +#define UNIPHY_PLL_CAL_CFG4        0x07C
>> +#define UNIPHY_PLL_CAL_CFG5        0x080
>> +#define UNIPHY_PLL_CAL_CFG6        0x084
>> +#define UNIPHY_PLL_CAL_CFG7        0x088
>> +#define UNIPHY_PLL_CAL_CFG8        0x08C
>> +#define UNIPHY_PLL_CAL_CFG9        0x090
>> +#define UNIPHY_PLL_CAL_CFG10        0x094
>> +#define UNIPHY_PLL_CAL_CFG11        0x098
>> +#define UNIPHY_PLL_EFUSE_CFG        0x09C
>> +#define UNIPHY_PLL_DEBUG_BUS_SEL    0x0A0
>> +#define UNIPHY_PLL_CTRL_42        0x0A4
>> +#define UNIPHY_PLL_CTRL_43        0x0A8
>> +#define UNIPHY_PLL_CTRL_44        0x0AC
>> +#define UNIPHY_PLL_CTRL_45        0x0B0
>> +#define UNIPHY_PLL_CTRL_46        0x0B4
>> +#define UNIPHY_PLL_CTRL_47        0x0B8
>> +#define UNIPHY_PLL_CTRL_48        0x0BC
>> +#define UNIPHY_PLL_STATUS        0x0C0
>> +#define UNIPHY_PLL_DEBUG_BUS0        0x0C4
>> +#define UNIPHY_PLL_DEBUG_BUS1        0x0C8
>> +#define UNIPHY_PLL_DEBUG_BUS2        0x0CC
>> +#define UNIPHY_PLL_DEBUG_BUS3        0x0D0
>> +#define UNIPHY_PLL_CTRL_54        0x0D4
>> +
>> +#define SATA_PHY_SER_CTRL        0x100
>> +#define SATA_PHY_TX_DRIV_CTRL0        0x104
>> +#define SATA_PHY_TX_DRIV_CTRL1        0x108
>> +#define SATA_PHY_TX_DRIV_CTRL2        0x10C
>> +#define SATA_PHY_TX_DRIV_CTRL3        0x110
>> +#define SATA_PHY_TX_IMCAL0        0x11C
>> +#define SATA_PHY_TX_IMCAL1        0x120
>> +#define SATA_PHY_TX_IMCAL2        0x124
>> +#define SATA_PHY_RX_IMCAL0        0x128
>> +#define SATA_PHY_RX_IMCAL1        0x12C
>> +#define SATA_PHY_RX_IMCAL2        0x130
>> +#define SATA_PHY_RX_TERM        0x134
>> +#define SATA_PHY_EQUAL            0x13C
>> +#define SATA_PHY_OOB_TERM        0x144
>> +#define SATA_PHY_CDR_CTRL0        0x148
>> +#define SATA_PHY_CDR_CTRL1        0x14C
>> +#define SATA_PHY_CDR_CTRL2        0x150
>> +#define SATA_PHY_CDR_CTRL3        0x154
>> +#define SATA_PHY_CDR_CTRL4        0x158
>> +#define SATA_PHY_FA_LOAD0        0x15C
>> +#define SATA_PHY_FA_LOAD1        0x160
>> +#define SATA_PHY_PI_CTRL0        0x168
>> +#define SATA_PHY_PI_CTRL1        0x16C
>> +#define SATA_PHY_AD_TPA_CTRL        0x178
>> +#define SATA_PHY_REFCLK_CTRL        0x17C
>> +#define SATA_PHY_POW_DWN_CTRL0        0x180
>> +#define SATA_PHY_POW_DWN_CTRL1        0x184
>> +#define SATA_PHY_TX_DATA_CTRL        0x188
>> +#define SATA_PHY_BIST_GEN0        0x18C
>> +#define SATA_PHY_BIST_GEN1        0x190
>> +#define SATA_PHY_BIST_GEN2        0x194
>> +#define SATA_PHY_BIST_GEN3        0x198
>> +#define SATA_PHY_LBK_CTRL        0x19C
>> +#define SATA_PHY_TEST_DEBUG_CTRL    0x1A0
>> +#define SATA_PHY_ALIGNP            0x1A4
>> +#define SATA_PHY_PRBS_CFG0        0x1A8
>> +#define SATA_PHY_PRBS_CFG1        0x1AC
>> +#define SATA_PHY_PRBS_CFG2        0x1B0
>> +#define SATA_PHY_PRBS_CFG3        0x1B4
>> +#define SATA_PHY_CHAN_COMP_CHK_CNT    0x1B8
>> +#define SATA_PHY_RESET_CTRL        0x1BC
>> +#define SATA_PHY_RX_CLR            0x1C0
>> +#define SATA_PHY_RX_EBUF_CTRL        0x1C4
>> +#define SATA_PHY_ID0            0x1C8
>> +#define SATA_PHY_ID1            0x1CC
>> +#define SATA_PHY_ID2            0x1D0
>> +#define SATA_PHY_ID3            0x1D4
>> +#define SATA_PHY_RX_CHK_ERR_CNT0    0x1D8
>> +#define SATA_PHY_RX_CHK_ERR_CNT1    0x1DC
>> +#define SATA_PHY_RX_CHK_STAT        0x1E0
>> +#define SATA_PHY_TX_IMCAL_STAT        0x1E4
>> +#define SATA_PHY_RX_IMCAL_STAT        0x1E8
>> +#define SATA_PHY_RX_EBUF_STAT        0x1EC
>> +#define SATA_PHY_DEBUG_BUS_STAT0    0x1F0
>> +#define SATA_PHY_DEBUG_BUS_STAT1    0x1F4
>> +#define SATA_PHY_DEBUG_BUS_STAT2    0x1F8
>> +#define SATA_PHY_DEBUG_BUS_STAT3    0x1FC
>> +
>> +#define UNIPHY_PLL_LOCK        BIT(0)
>> +#define SATA_PHY_TX_CAL        BIT(0)
>> +#define SATA_PHY_RX_CAL        BIT(0)
>> +
>> +/* default timeout set to 1 sec */
>> +#define TIMEOUT_MS        10000
>> +
>> +struct qcom_apq8064_sata_phy {
>> +    void __iomem *mmio;
>> +    struct clk *cfg_clk;
>> +    struct device *dev;
>> +};
>> +
>> +/* Helper function to do poll and timeout */
>> +static int read_poll_timeout(void __iomem *addr, u32 mask)
>> +{
>> +    unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
>> +    u32 val;
>> +
>> +    do {
>> +        cpu_relax();
>> +        val = readl_relaxed(addr);
>> +        if (val & mask)
>> +            break;
>> +    } while (!time_after(jiffies, timeout));
>> +
>> +    return (val & mask) ? 0 : -ETIMEDOUT;
>> +}
>> +
>> +static int qcom_apq8064_sata_phy_init(struct phy *generic_phy)
>> +{
>> +    struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
>> +    void __iomem *base = phy->mmio;
>> +    int ret = 0;
>> +
>> +    /* SATA phy initialization */
>> +    writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
>> +    writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
>> +    /* Make sure the power down happens before power up */
>> +    mb();
>> +    usleep_range(10, 60);
>> +
>> +    writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
>> +    writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
>> +    writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
>> +    writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
>> +    writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
>> +
>> +    /* Write UNIPHYPLL registers to configure PLL */
>> +    writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
>> +    writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG);
>> +
>> +    writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0);
>> +    writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8);
>> +    writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9);
>> +    writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10);
>> +    writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11);
>> +
>> +    writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0);
>> +    writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1);
>> +    writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2);
>> +    writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3);
>> +    writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4);
>> +
>> +    writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0);
>> +    writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1);
>> +    writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2);
>> +    writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3);
>> +
>> +    writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0);
>> +    writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1);
>> +
>> +    writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG);
>> +    /* make sure global config LDO power down happens before power up */
>> +    mb();
>> +
>> +    writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG);
>> +    writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2);
>> +
>> +    /* PLL Lock wait */
>> +    ret = read_poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK);
>> +    if (ret) {
>> +        dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n");
>> +        return ret;
>> +    }
>> +
>> +    /* TX Calibration */
>> +    ret = read_poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL);
>> +    if (ret) {
>> +        dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n");
>> +        return ret;
>> +    }
>> +
>> +    /* RX Calibration */
>> +    ret = read_poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL);
>> +    if (ret) {
>> +        dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n");
>> +        return ret;
>> +    }
>> +
>> +    /* SATA phy calibrated succesfully, power up to functional mode */
>> +    writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
>> +    writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
>> +    writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
>> +
>> +    writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1);
>> +    writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0);
>> +    writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1);
>> +    writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2);
>> +    writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0);
>> +    writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3);
>> +    writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
>> +
>> +    writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL);
>> +    writel_relaxed(0x43, base + SATA_PHY_ALIGNP);
>> +    writel_relaxed(0x04, base + SATA_PHY_OOB_TERM);
>> +
>> +    writel_relaxed(0x01, base + SATA_PHY_EQUAL);
>> +    writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0);
>> +    writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1);
>> +
>> +    return 0;
>> +}
>> +
>> +static int qcom_apq8064_sata_phy_exit(struct phy *generic_phy)
>> +{
>> +    struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
>> +    void __iomem *base = phy->mmio;
>> +
>> +    /* Power down PHY */
>> +    writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0);
>> +    writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1);
>> +
>> +    /* Power down PLL block */
>> +    writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG);
>> +
>> +    return 0;
>> +}
>> +
>> +static struct phy_ops qcom_apq8064_sata_phy_ops = {
>> +    .init        = qcom_apq8064_sata_phy_init,
>> +    .exit        = qcom_apq8064_sata_phy_exit,
>> +    .owner        = THIS_MODULE,
>> +};
>> +
>> +static int qcom_apq8064_sata_phy_probe(struct platform_device *pdev)
>> +{
>> +    struct qcom_apq8064_sata_phy *phy;
>> +    struct device *dev = &pdev->dev;
>> +    struct resource *res;
>> +    struct phy_provider *phy_provider;
>> +    struct phy *generic_phy;
>> +    int ret;
>> +
>> +    phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
>> +    if (!phy)
>> +        return -ENOMEM;
>> +
>> +    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +    phy->mmio = devm_ioremap_resource(dev, res);
>> +    if (IS_ERR(phy->mmio))
>> +        return PTR_ERR(phy->mmio);
>> +
>> +    generic_phy = devm_phy_create(dev, &qcom_apq8064_sata_phy_ops, NULL);
>> +    if (IS_ERR(generic_phy)) {
>> +        dev_err(dev, "%s: failed to create phy\n", __func__);
>> +        return PTR_ERR(generic_phy);
>> +    }
>> +
>> +    phy->dev = dev;
>> +    phy_set_drvdata(generic_phy, phy);
>> +
>> +    phy->cfg_clk = devm_clk_get(dev, "cfg");
>> +    if (IS_ERR(phy->cfg_clk)) {
>> +        dev_err(dev, "Failed to get sata cfg clock\n");
>> +        return PTR_ERR(phy->cfg_clk);
>> +    }
>> +
>> +    ret = clk_prepare_enable(phy->cfg_clk);
>> +    if (ret)
>> +        return ret;
>> +
>> +    phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> +    if (IS_ERR(phy_provider)) {
>> +        clk_disable_unprepare(phy->cfg_clk);
>> +        dev_err(dev, "%s: failed to register phy\n", __func__);
>> +        return PTR_ERR(phy_provider);
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +static int qcom_apq8064_sata_phy_remove(struct platform_device *pdev)
>> +{
>> +    struct qcom_apq8064_sata_phy *phy = platform_get_drvdata(pdev);
>> +
>> +    clk_disable_unprepare(phy->cfg_clk);
>> +
>> +    return 0;
>> +}
>> +
>> +static const struct of_device_id qcom_apq8064_sata_phy_of_match[] = {
>> +    { .compatible = "qcom,apq8064-sata-phy" },
>> +    { },
>> +};
>> +MODULE_DEVICE_TABLE(of, qcom_apq8064_sata_phy_of_match);
>> +
>> +static struct platform_driver qcom_apq8064_sata_phy_driver = {
>> +    .probe    = qcom_apq8064_sata_phy_probe,
>> +    .remove    = qcom_apq8064_sata_phy_remove,
>> +    .driver = {
>> +        .name    = "qcom-apq8064-sata-phy",
>> +        .owner    = THIS_MODULE,
>> +        .of_match_table    = qcom_apq8064_sata_phy_of_match,
>> +    }
>> +};
>> +module_platform_driver(qcom_apq8064_sata_phy_driver);
>> +
>> +MODULE_DESCRIPTION("QCOM apq8064 SATA PHY driver");
>> +MODULE_LICENSE("GPL v2");
>>

[PATCH v2 0/2] Add Qcom AP8064 SATA PHY support

[Srinivas Kandagatla]

Hi Kishon,

First patch in this series adds support to the APQ8064 SATA PHY.
Second patch updates the existing Kumar gala's device tree PHY bindings
with APQ8064 soc specific compatible.

Eventhough there are two seperate drivers for both IPQ and APQ SOCs,
the bindings are exactly same, so I did not create new bindings document.

Could you please pick these patches for v3.17.

Changes since v1:
	- included DT bindings in the series.

Thanks,
srini

Srinivas Kandagatla (2):
  phy: qcom: Add driver for QCOM APQ8064 SATA PHY
  phy: qcom: Update APQ8064 PHY device tree bindings

 Documentation/devicetree/bindings/phy/qcom-phy.txt |   3 +-
 drivers/phy/Kconfig                                |   7 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-qcom-apq8064-sata.c                | 358 +++++++++++++++++++++
 4 files changed, 368 insertions(+), 1 deletion(-)
 create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c

-- 
1.9.1

[PATCH v2 1/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Srinivas Kandagatla]

Add a PHY driver for uses with AHCI based SATA controller driver on the
APQ8064 family of SoCs.

This patch is a forward port from Qualcomm's v3.4 andriod kernel.

Tested on IFC6410 board.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 drivers/phy/Kconfig                 |   7 +
 drivers/phy/Makefile                |   1 +
 drivers/phy/phy-qcom-apq8064-sata.c | 358 ++++++++++++++++++++++++++++++++++++
 3 files changed, 366 insertions(+)
 create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index b7b6bce..39083c7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,6 +178,13 @@ config PHY_XGENE
 	help
 	  This option enables support for APM X-Gene SoC multi-purpose PHY.
 
+config PHY_QCOM_APQ8064_SATA
+	tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
+	depends on ARCH_QCOM
+	depends on HAS_IOMEM
+	depends on OF
+	select GENERIC_PHY
+
 config PHY_QCOM_IPQ806X_SATA
 	tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
 	depends on ARCH_QCOM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d950317..8782088 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,4 +20,5 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-apq8064-sata.c b/drivers/phy/phy-qcom-apq8064-sata.c
new file mode 100644
index 0000000..e9e59e2
--- /dev/null
+++ b/drivers/phy/phy-qcom-apq8064-sata.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+
+/* PHY registers */
+#define UNIPHY_PLL_REFCLK_CFG		0x000
+#define UNIPHY_PLL_POSTDIV1_CFG		0x004
+#define UNIPHY_PLL_CHGPUMP_CFG		0x008
+#define UNIPHY_PLL_VCOLPF_CFG		0x00C
+#define UNIPHY_PLL_VREG_CFG		0x010
+#define UNIPHY_PLL_PWRGEN_CFG		0x014
+#define UNIPHY_PLL_DMUX_CFG		0x018
+#define UNIPHY_PLL_AMUX_CFG		0x01C
+#define UNIPHY_PLL_GLB_CFG		0x020
+#define UNIPHY_PLL_POSTDIV2_CFG		0x024
+#define UNIPHY_PLL_POSTDIV3_CFG		0x028
+#define UNIPHY_PLL_LPFR_CFG		0x02C
+#define UNIPHY_PLL_LPFC1_CFG		0x030
+#define UNIPHY_PLL_LPFC2_CFG		0x034
+#define UNIPHY_PLL_SDM_CFG0		0x038
+#define UNIPHY_PLL_SDM_CFG1		0x03C
+#define UNIPHY_PLL_SDM_CFG2		0x040
+#define UNIPHY_PLL_SDM_CFG3		0x044
+#define UNIPHY_PLL_SDM_CFG4		0x048
+#define UNIPHY_PLL_SSC_CFG0		0x04C
+#define UNIPHY_PLL_SSC_CFG1		0x050
+#define UNIPHY_PLL_SSC_CFG2		0x054
+#define UNIPHY_PLL_SSC_CFG3		0x058
+#define UNIPHY_PLL_LKDET_CFG0		0x05C
+#define UNIPHY_PLL_LKDET_CFG1		0x060
+#define UNIPHY_PLL_LKDET_CFG2		0x064
+#define UNIPHY_PLL_TEST_CFG		0x068
+#define UNIPHY_PLL_CAL_CFG0		0x06C
+#define UNIPHY_PLL_CAL_CFG1		0x070
+#define UNIPHY_PLL_CAL_CFG2		0x074
+#define UNIPHY_PLL_CAL_CFG3		0x078
+#define UNIPHY_PLL_CAL_CFG4		0x07C
+#define UNIPHY_PLL_CAL_CFG5		0x080
+#define UNIPHY_PLL_CAL_CFG6		0x084
+#define UNIPHY_PLL_CAL_CFG7		0x088
+#define UNIPHY_PLL_CAL_CFG8		0x08C
+#define UNIPHY_PLL_CAL_CFG9		0x090
+#define UNIPHY_PLL_CAL_CFG10		0x094
+#define UNIPHY_PLL_CAL_CFG11		0x098
+#define UNIPHY_PLL_EFUSE_CFG		0x09C
+#define UNIPHY_PLL_DEBUG_BUS_SEL	0x0A0
+#define UNIPHY_PLL_CTRL_42		0x0A4
+#define UNIPHY_PLL_CTRL_43		0x0A8
+#define UNIPHY_PLL_CTRL_44		0x0AC
+#define UNIPHY_PLL_CTRL_45		0x0B0
+#define UNIPHY_PLL_CTRL_46		0x0B4
+#define UNIPHY_PLL_CTRL_47		0x0B8
+#define UNIPHY_PLL_CTRL_48		0x0BC
+#define UNIPHY_PLL_STATUS		0x0C0
+#define UNIPHY_PLL_DEBUG_BUS0		0x0C4
+#define UNIPHY_PLL_DEBUG_BUS1		0x0C8
+#define UNIPHY_PLL_DEBUG_BUS2		0x0CC
+#define UNIPHY_PLL_DEBUG_BUS3		0x0D0
+#define UNIPHY_PLL_CTRL_54		0x0D4
+
+#define SATA_PHY_SER_CTRL		0x100
+#define SATA_PHY_TX_DRIV_CTRL0		0x104
+#define SATA_PHY_TX_DRIV_CTRL1		0x108
+#define SATA_PHY_TX_DRIV_CTRL2		0x10C
+#define SATA_PHY_TX_DRIV_CTRL3		0x110
+#define SATA_PHY_TX_IMCAL0		0x11C
+#define SATA_PHY_TX_IMCAL1		0x120
+#define SATA_PHY_TX_IMCAL2		0x124
+#define SATA_PHY_RX_IMCAL0		0x128
+#define SATA_PHY_RX_IMCAL1		0x12C
+#define SATA_PHY_RX_IMCAL2		0x130
+#define SATA_PHY_RX_TERM		0x134
+#define SATA_PHY_EQUAL			0x13C
+#define SATA_PHY_OOB_TERM		0x144
+#define SATA_PHY_CDR_CTRL0		0x148
+#define SATA_PHY_CDR_CTRL1		0x14C
+#define SATA_PHY_CDR_CTRL2		0x150
+#define SATA_PHY_CDR_CTRL3		0x154
+#define SATA_PHY_CDR_CTRL4		0x158
+#define SATA_PHY_FA_LOAD0		0x15C
+#define SATA_PHY_FA_LOAD1		0x160
+#define SATA_PHY_PI_CTRL0		0x168
+#define SATA_PHY_PI_CTRL1		0x16C
+#define SATA_PHY_AD_TPA_CTRL		0x178
+#define SATA_PHY_REFCLK_CTRL		0x17C
+#define SATA_PHY_POW_DWN_CTRL0		0x180
+#define SATA_PHY_POW_DWN_CTRL1		0x184
+#define SATA_PHY_TX_DATA_CTRL		0x188
+#define SATA_PHY_BIST_GEN0		0x18C
+#define SATA_PHY_BIST_GEN1		0x190
+#define SATA_PHY_BIST_GEN2		0x194
+#define SATA_PHY_BIST_GEN3		0x198
+#define SATA_PHY_LBK_CTRL		0x19C
+#define SATA_PHY_TEST_DEBUG_CTRL	0x1A0
+#define SATA_PHY_ALIGNP			0x1A4
+#define SATA_PHY_PRBS_CFG0		0x1A8
+#define SATA_PHY_PRBS_CFG1		0x1AC
+#define SATA_PHY_PRBS_CFG2		0x1B0
+#define SATA_PHY_PRBS_CFG3		0x1B4
+#define SATA_PHY_CHAN_COMP_CHK_CNT	0x1B8
+#define SATA_PHY_RESET_CTRL		0x1BC
+#define SATA_PHY_RX_CLR			0x1C0
+#define SATA_PHY_RX_EBUF_CTRL		0x1C4
+#define SATA_PHY_ID0			0x1C8
+#define SATA_PHY_ID1			0x1CC
+#define SATA_PHY_ID2			0x1D0
+#define SATA_PHY_ID3			0x1D4
+#define SATA_PHY_RX_CHK_ERR_CNT0	0x1D8
+#define SATA_PHY_RX_CHK_ERR_CNT1	0x1DC
+#define SATA_PHY_RX_CHK_STAT		0x1E0
+#define SATA_PHY_TX_IMCAL_STAT		0x1E4
+#define SATA_PHY_RX_IMCAL_STAT		0x1E8
+#define SATA_PHY_RX_EBUF_STAT		0x1EC
+#define SATA_PHY_DEBUG_BUS_STAT0	0x1F0
+#define SATA_PHY_DEBUG_BUS_STAT1	0x1F4
+#define SATA_PHY_DEBUG_BUS_STAT2	0x1F8
+#define SATA_PHY_DEBUG_BUS_STAT3	0x1FC
+
+#define UNIPHY_PLL_LOCK		BIT(0)
+#define SATA_PHY_TX_CAL		BIT(0)
+#define SATA_PHY_RX_CAL		BIT(0)
+
+/* default timeout set to 1 sec */
+#define TIMEOUT_MS		10000
+
+struct qcom_apq8064_sata_phy {
+	void __iomem *mmio;
+	struct clk *cfg_clk;
+	struct device *dev;
+};
+
+/* Helper function to do poll and timeout */
+static int read_poll_timeout(void __iomem *addr, u32 mask)
+{
+	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
+	u32 val;
+
+	do {
+		cpu_relax();
+		val = readl_relaxed(addr);
+		if (val & mask)
+			break;
+	} while (!time_after(jiffies, timeout));
+
+	return (val & mask) ? 0 : -ETIMEDOUT;
+}
+
+static int qcom_apq8064_sata_phy_init(struct phy *generic_phy)
+{
+	struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
+	void __iomem *base = phy->mmio;
+	int ret = 0;
+
+	/* SATA phy initialization */
+	writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
+	writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
+	/* Make sure the power down happens before power up */
+	mb();
+	usleep_range(10, 60);
+
+	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
+	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
+	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
+	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
+	writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
+
+	/* Write UNIPHYPLL registers to configure PLL */
+	writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
+	writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG);
+
+	writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0);
+	writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8);
+	writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9);
+	writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10);
+	writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11);
+
+	writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0);
+	writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1);
+	writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2);
+	writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3);
+	writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4);
+
+	writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0);
+	writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1);
+	writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2);
+	writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3);
+
+	writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0);
+	writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1);
+
+	writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG);
+	/* make sure global config LDO power down happens before power up */
+	mb();
+
+	writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG);
+	writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2);
+
+	/* PLL Lock wait */
+	ret = read_poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK);
+	if (ret) {
+		dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n");
+		return ret;
+	}
+
+	/* TX Calibration */
+	ret = read_poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL);
+	if (ret) {
+		dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n");
+		return ret;
+	}
+
+	/* RX Calibration */
+	ret = read_poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL);
+	if (ret) {
+		dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n");
+		return ret;
+	}
+
+	/* SATA phy calibrated succesfully, power up to functional mode */
+	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
+	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
+	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
+
+	writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1);
+	writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0);
+	writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1);
+	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2);
+	writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0);
+	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3);
+	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
+
+	writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL);
+	writel_relaxed(0x43, base + SATA_PHY_ALIGNP);
+	writel_relaxed(0x04, base + SATA_PHY_OOB_TERM);
+
+	writel_relaxed(0x01, base + SATA_PHY_EQUAL);
+	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0);
+	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1);
+
+	return 0;
+}
+
+static int qcom_apq8064_sata_phy_exit(struct phy *generic_phy)
+{
+	struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
+	void __iomem *base = phy->mmio;
+
+	/* Power down PHY */
+	writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0);
+	writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1);
+
+	/* Power down PLL block */
+	writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG);
+
+	return 0;
+}
+
+static struct phy_ops qcom_apq8064_sata_phy_ops = {
+	.init		= qcom_apq8064_sata_phy_init,
+	.exit		= qcom_apq8064_sata_phy_exit,
+	.owner		= THIS_MODULE,
+};
+
+static int qcom_apq8064_sata_phy_probe(struct platform_device *pdev)
+{
+	struct qcom_apq8064_sata_phy *phy;
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct phy_provider *phy_provider;
+	struct phy *generic_phy;
+	int ret;
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	phy->mmio = devm_ioremap_resource(dev, res);
+	if (IS_ERR(phy->mmio))
+		return PTR_ERR(phy->mmio);
+
+	generic_phy = devm_phy_create(dev, &qcom_apq8064_sata_phy_ops, NULL);
+	if (IS_ERR(generic_phy)) {
+		dev_err(dev, "%s: failed to create phy\n", __func__);
+		return PTR_ERR(generic_phy);
+	}
+
+	phy->dev = dev;
+	phy_set_drvdata(generic_phy, phy);
+
+	phy->cfg_clk = devm_clk_get(dev, "cfg");
+	if (IS_ERR(phy->cfg_clk)) {
+		dev_err(dev, "Failed to get sata cfg clock\n");
+		return PTR_ERR(phy->cfg_clk);
+	}
+
+	ret = clk_prepare_enable(phy->cfg_clk);
+	if (ret)
+		return ret;
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(phy_provider)) {
+		clk_disable_unprepare(phy->cfg_clk);
+		dev_err(dev, "%s: failed to register phy\n", __func__);
+		return PTR_ERR(phy_provider);
+	}
+
+	return 0;
+}
+
+static int qcom_apq8064_sata_phy_remove(struct platform_device *pdev)
+{
+	struct qcom_apq8064_sata_phy *phy = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(phy->cfg_clk);
+
+	return 0;
+}
+
+static const struct of_device_id qcom_apq8064_sata_phy_of_match[] = {
+	{ .compatible = "qcom,apq8064-sata-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, qcom_apq8064_sata_phy_of_match);
+
+static struct platform_driver qcom_apq8064_sata_phy_driver = {
+	.probe	= qcom_apq8064_sata_phy_probe,
+	.remove	= qcom_apq8064_sata_phy_remove,
+	.driver = {
+		.name	= "qcom-apq8064-sata-phy",
+		.owner	= THIS_MODULE,
+		.of_match_table	= qcom_apq8064_sata_phy_of_match,
+	}
+};
+module_platform_driver(qcom_apq8064_sata_phy_driver);
+
+MODULE_DESCRIPTION("QCOM apq8064 SATA PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

[PATCH v2 2/2] phy: qcom: Update APQ8064 PHY device tree bindings

[Srinivas Kandagatla]

Update binding spec for Qualcomm SoC PHYs with APQ8064 compatibles.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 Documentation/devicetree/bindings/phy/qcom-phy.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/qcom-phy.txt b/Documentation/devicetree/bindings/phy/qcom-phy.txt
index 76bfbd0..6bff1e0 100644
--- a/Documentation/devicetree/bindings/phy/qcom-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-phy.txt
@@ -1,4 +1,4 @@
-Qualcomm IPQ806x SATA PHY Controller
+Qualcomm IPQ806x/APQ8064 SATA PHY Controller
 ------------------------------------
 
 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
@@ -6,6 +6,7 @@ Each SATA PHY controller should have its own node.
 
 Required properties:
 - compatible: compatible list, contains "qcom,ipq806x-sata-phy"
+	     or "qcom,apq8064-sata-phy".
 - reg: offset and length of the SATA PHY register set;
 - #phy-cells: must be zero
 - clocks: must be exactly one entry
-- 
1.9.1

Re: [PATCH v2 1/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Bartlomiej Zolnierkiewicz]

Hi,

On Wednesday, July 09, 2014 12:04:06 PM Srinivas Kandagatla wrote:
> Add a PHY driver for uses with AHCI based SATA controller driver on the
> APQ8064 family of SoCs.
> 
> This patch is a forward port from Qualcomm's v3.4 andriod kernel.

Android?

> Tested on IFC6410 board.
> 
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> ---
>  drivers/phy/Kconfig                 |   7 +
>  drivers/phy/Makefile                |   1 +
>  drivers/phy/phy-qcom-apq8064-sata.c | 358 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 366 insertions(+)
>  create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index b7b6bce..39083c7 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -178,6 +178,13 @@ config PHY_XGENE
>  	help
>  	  This option enables support for APM X-Gene SoC multi-purpose PHY.
>  
> +config PHY_QCOM_APQ8064_SATA
> +	tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
> +	depends on ARCH_QCOM
> +	depends on HAS_IOMEM
> +	depends on OF
> +	select GENERIC_PHY
> +
>  config PHY_QCOM_IPQ806X_SATA
>  	tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
>  	depends on ARCH_QCOM
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index d950317..8782088 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -20,4 +20,5 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o
>  phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>  obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o
> +obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
> diff --git a/drivers/phy/phy-qcom-apq8064-sata.c b/drivers/phy/phy-qcom-apq8064-sata.c
> new file mode 100644
> index 0000000..e9e59e2
> --- /dev/null
> +++ b/drivers/phy/phy-qcom-apq8064-sata.c
> @@ -0,0 +1,358 @@
> +/*
> + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/time.h>
> +#include <linux/delay.h>
> +#include <linux/clk.h>
> +#include <linux/slab.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +
> +/* PHY registers */
> +#define UNIPHY_PLL_REFCLK_CFG		0x000
> +#define UNIPHY_PLL_POSTDIV1_CFG		0x004

unused define, please remove it

> +#define UNIPHY_PLL_CHGPUMP_CFG		0x008

ditto

> +#define UNIPHY_PLL_VCOLPF_CFG		0x00C

ditto

> +#define UNIPHY_PLL_VREG_CFG		0x010

ditto

> +#define UNIPHY_PLL_PWRGEN_CFG		0x014
> +#define UNIPHY_PLL_DMUX_CFG		0x018

ditto

> +#define UNIPHY_PLL_AMUX_CFG		0x01C

ditto

> +#define UNIPHY_PLL_GLB_CFG		0x020
> +#define UNIPHY_PLL_POSTDIV2_CFG		0x024

ditto

> +#define UNIPHY_PLL_POSTDIV3_CFG		0x028

ditto

> +#define UNIPHY_PLL_LPFR_CFG		0x02C

ditto

> +#define UNIPHY_PLL_LPFC1_CFG		0x030

ditto

> +#define UNIPHY_PLL_LPFC2_CFG		0x034

ditto

> +#define UNIPHY_PLL_SDM_CFG0		0x038
> +#define UNIPHY_PLL_SDM_CFG1		0x03C
> +#define UNIPHY_PLL_SDM_CFG2		0x040
> +#define UNIPHY_PLL_SDM_CFG3		0x044
> +#define UNIPHY_PLL_SDM_CFG4		0x048
> +#define UNIPHY_PLL_SSC_CFG0		0x04C
> +#define UNIPHY_PLL_SSC_CFG1		0x050
> +#define UNIPHY_PLL_SSC_CFG2		0x054
> +#define UNIPHY_PLL_SSC_CFG3		0x058
> +#define UNIPHY_PLL_LKDET_CFG0		0x05C
> +#define UNIPHY_PLL_LKDET_CFG1		0x060
> +#define UNIPHY_PLL_LKDET_CFG2		0x064
> +#define UNIPHY_PLL_TEST_CFG		0x068

ditto

> +#define UNIPHY_PLL_CAL_CFG0		0x06C
> +#define UNIPHY_PLL_CAL_CFG1		0x070

ditto

> +#define UNIPHY_PLL_CAL_CFG2		0x074

ditto

> +#define UNIPHY_PLL_CAL_CFG3		0x078

ditto

> +#define UNIPHY_PLL_CAL_CFG4		0x07C

ditto

> +#define UNIPHY_PLL_CAL_CFG5		0x080

ditto

> +#define UNIPHY_PLL_CAL_CFG6		0x084

ditto

> +#define UNIPHY_PLL_CAL_CFG7		0x088

ditto

> +#define UNIPHY_PLL_CAL_CFG8		0x08C
> +#define UNIPHY_PLL_CAL_CFG9		0x090
> +#define UNIPHY_PLL_CAL_CFG10		0x094
> +#define UNIPHY_PLL_CAL_CFG11		0x098
> +#define UNIPHY_PLL_EFUSE_CFG		0x09C

ditto

> +#define UNIPHY_PLL_DEBUG_BUS_SEL	0x0A0

ditto

> +#define UNIPHY_PLL_CTRL_42		0x0A4

ditto

> +#define UNIPHY_PLL_CTRL_43		0x0A8

ditto

> +#define UNIPHY_PLL_CTRL_44		0x0AC

ditto

> +#define UNIPHY_PLL_CTRL_45		0x0B0

ditto

> +#define UNIPHY_PLL_CTRL_46		0x0B4

ditto

> +#define UNIPHY_PLL_CTRL_47		0x0B8

ditto

> +#define UNIPHY_PLL_CTRL_48		0x0BC

ditto

> +#define UNIPHY_PLL_STATUS		0x0C0
> +#define UNIPHY_PLL_DEBUG_BUS0		0x0C4

ditto

> +#define UNIPHY_PLL_DEBUG_BUS1		0x0C8

ditto

> +#define UNIPHY_PLL_DEBUG_BUS2		0x0CC

ditto

> +#define UNIPHY_PLL_DEBUG_BUS3		0x0D0

ditto

> +#define UNIPHY_PLL_CTRL_54		0x0D4

ditto

> +
> +#define SATA_PHY_SER_CTRL		0x100
> +#define SATA_PHY_TX_DRIV_CTRL0		0x104
> +#define SATA_PHY_TX_DRIV_CTRL1		0x108
> +#define SATA_PHY_TX_DRIV_CTRL2		0x10C

ditto

> +#define SATA_PHY_TX_DRIV_CTRL3		0x110

ditto

> +#define SATA_PHY_TX_IMCAL0		0x11C
> +#define SATA_PHY_TX_IMCAL1		0x120

ditto

> +#define SATA_PHY_TX_IMCAL2		0x124
> +#define SATA_PHY_RX_IMCAL0		0x128
> +#define SATA_PHY_RX_IMCAL1		0x12C

ditto

> +#define SATA_PHY_RX_IMCAL2		0x130

ditto

> +#define SATA_PHY_RX_TERM		0x134

ditto

> +#define SATA_PHY_EQUAL			0x13C
> +#define SATA_PHY_OOB_TERM		0x144
> +#define SATA_PHY_CDR_CTRL0		0x148
> +#define SATA_PHY_CDR_CTRL1		0x14C
> +#define SATA_PHY_CDR_CTRL2		0x150
> +#define SATA_PHY_CDR_CTRL3		0x154
> +#define SATA_PHY_CDR_CTRL4		0x158

ditto

> +#define SATA_PHY_FA_LOAD0		0x15C

ditto

> +#define SATA_PHY_FA_LOAD1		0x160

ditto

> +#define SATA_PHY_PI_CTRL0		0x168
> +#define SATA_PHY_PI_CTRL1		0x16C

ditto

> +#define SATA_PHY_AD_TPA_CTRL		0x178

ditto

> +#define SATA_PHY_REFCLK_CTRL		0x17C

ditto

> +#define SATA_PHY_POW_DWN_CTRL0		0x180
> +#define SATA_PHY_POW_DWN_CTRL1		0x184
> +#define SATA_PHY_TX_DATA_CTRL		0x188
> +#define SATA_PHY_BIST_GEN0		0x18C

ditto

> +#define SATA_PHY_BIST_GEN1		0x190

ditto

> +#define SATA_PHY_BIST_GEN2		0x194

ditto

> +#define SATA_PHY_BIST_GEN3		0x198

ditto

> +#define SATA_PHY_LBK_CTRL		0x19C

ditto

> +#define SATA_PHY_TEST_DEBUG_CTRL	0x1A0

ditto

> +#define SATA_PHY_ALIGNP			0x1A4
> +#define SATA_PHY_PRBS_CFG0		0x1A8

ditto

> +#define SATA_PHY_PRBS_CFG1		0x1AC

ditto

> +#define SATA_PHY_PRBS_CFG2		0x1B0

ditto

> +#define SATA_PHY_PRBS_CFG3		0x1B4

ditto

> +#define SATA_PHY_CHAN_COMP_CHK_CNT	0x1B8

ditto

> +#define SATA_PHY_RESET_CTRL		0x1BC

ditto

> +#define SATA_PHY_RX_CLR			0x1C0

ditto

> +#define SATA_PHY_RX_EBUF_CTRL		0x1C4

ditto

> +#define SATA_PHY_ID0			0x1C8

ditto

> +#define SATA_PHY_ID1			0x1CC

ditto

> +#define SATA_PHY_ID2			0x1D0

ditto

> +#define SATA_PHY_ID3			0x1D4

ditto

> +#define SATA_PHY_RX_CHK_ERR_CNT0	0x1D8

ditto

> +#define SATA_PHY_RX_CHK_ERR_CNT1	0x1DC

ditto

> +#define SATA_PHY_RX_CHK_STAT		0x1E0

ditto

> +#define SATA_PHY_TX_IMCAL_STAT		0x1E4
> +#define SATA_PHY_RX_IMCAL_STAT		0x1E8
> +#define SATA_PHY_RX_EBUF_STAT		0x1EC

ditto

> +#define SATA_PHY_DEBUG_BUS_STAT0	0x1F0

ditto

> +#define SATA_PHY_DEBUG_BUS_STAT1	0x1F4

ditto

> +#define SATA_PHY_DEBUG_BUS_STAT2	0x1F8

ditto

> +#define SATA_PHY_DEBUG_BUS_STAT3	0x1FC

ditto

> +
> +#define UNIPHY_PLL_LOCK		BIT(0)
> +#define SATA_PHY_TX_CAL		BIT(0)
> +#define SATA_PHY_RX_CAL		BIT(0)
> +
> +/* default timeout set to 1 sec */
> +#define TIMEOUT_MS		10000
> +
> +struct qcom_apq8064_sata_phy {
> +	void __iomem *mmio;
> +	struct clk *cfg_clk;
> +	struct device *dev;
> +};
> +
> +/* Helper function to do poll and timeout */
> +static int read_poll_timeout(void __iomem *addr, u32 mask)
> +{
> +	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
> +	u32 val;
> +
> +	do {
> +		cpu_relax();
> +		val = readl_relaxed(addr);
> +		if (val & mask)
> +			break;
> +	} while (!time_after(jiffies, timeout));

It would be better to use usleep_[range]() (or even msleep() if needed)
instead of just using cpu_relax().

> +
> +	return (val & mask) ? 0 : -ETIMEDOUT;
> +}
> +
> +static int qcom_apq8064_sata_phy_init(struct phy *generic_phy)
> +{
> +	struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
> +	void __iomem *base = phy->mmio;
> +	int ret = 0;
> +
> +	/* SATA phy initialization */
> +	writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
> +	writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
> +	/* Make sure the power down happens before power up */
> +	mb();
> +	usleep_range(10, 60);
> +
> +	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
> +	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
> +	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
> +	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
> +	writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
> +
> +	/* Write UNIPHYPLL registers to configure PLL */
> +	writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
> +	writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG);
> +
> +	writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0);
> +	writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8);
> +	writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9);
> +	writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10);
> +	writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11);
> +
> +	writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0);
> +	writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1);
> +	writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2);
> +	writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3);
> +	writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4);
> +
> +	writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0);
> +	writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1);
> +	writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2);
> +	writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3);
> +
> +	writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0);
> +	writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1);
> +
> +	writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG);
> +	/* make sure global config LDO power down happens before power up */
> +	mb();
> +
> +	writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG);
> +	writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2);
> +
> +	/* PLL Lock wait */
> +	ret = read_poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK);
> +	if (ret) {
> +		dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n");
> +		return ret;
> +	}
> +
> +	/* TX Calibration */
> +	ret = read_poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL);
> +	if (ret) {
> +		dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n");
> +		return ret;
> +	}
> +
> +	/* RX Calibration */
> +	ret = read_poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL);
> +	if (ret) {
> +		dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n");
> +		return ret;
> +	}
> +
> +	/* SATA phy calibrated succesfully, power up to functional mode */
> +	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
> +	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
> +	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
> +
> +	writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1);
> +	writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0);
> +	writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1);
> +	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2);
> +	writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0);
> +	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3);
> +	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
> +
> +	writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL);
> +	writel_relaxed(0x43, base + SATA_PHY_ALIGNP);
> +	writel_relaxed(0x04, base + SATA_PHY_OOB_TERM);
> +
> +	writel_relaxed(0x01, base + SATA_PHY_EQUAL);
> +	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0);
> +	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1);
> +
> +	return 0;
> +}
> +
> +static int qcom_apq8064_sata_phy_exit(struct phy *generic_phy)
> +{
> +	struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
> +	void __iomem *base = phy->mmio;
> +
> +	/* Power down PHY */
> +	writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0);
> +	writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1);
> +
> +	/* Power down PLL block */
> +	writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG);
> +
> +	return 0;
> +}
> +
> +static struct phy_ops qcom_apq8064_sata_phy_ops = {
> +	.init		= qcom_apq8064_sata_phy_init,
> +	.exit		= qcom_apq8064_sata_phy_exit,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int qcom_apq8064_sata_phy_probe(struct platform_device *pdev)
> +{
> +	struct qcom_apq8064_sata_phy *phy;
> +	struct device *dev = &pdev->dev;
> +	struct resource *res;
> +	struct phy_provider *phy_provider;
> +	struct phy *generic_phy;
> +	int ret;
> +
> +	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
> +	if (!phy)
> +		return -ENOMEM;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	phy->mmio = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(phy->mmio))
> +		return PTR_ERR(phy->mmio);
> +
> +	generic_phy = devm_phy_create(dev, &qcom_apq8064_sata_phy_ops, NULL);
> +	if (IS_ERR(generic_phy)) {
> +		dev_err(dev, "%s: failed to create phy\n", __func__);
> +		return PTR_ERR(generic_phy);
> +	}
> +
> +	phy->dev = dev;
> +	phy_set_drvdata(generic_phy, phy);
> +
> +	phy->cfg_clk = devm_clk_get(dev, "cfg");
> +	if (IS_ERR(phy->cfg_clk)) {
> +		dev_err(dev, "Failed to get sata cfg clock\n");
> +		return PTR_ERR(phy->cfg_clk);
> +	}
> +
> +	ret = clk_prepare_enable(phy->cfg_clk);
> +	if (ret)
> +		return ret;
> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider)) {
> +		clk_disable_unprepare(phy->cfg_clk);
> +		dev_err(dev, "%s: failed to register phy\n", __func__);
> +		return PTR_ERR(phy_provider);
> +	}
> +
> +	return 0;
> +}
> +
> +static int qcom_apq8064_sata_phy_remove(struct platform_device *pdev)
> +{
> +	struct qcom_apq8064_sata_phy *phy = platform_get_drvdata(pdev);

Doesn't this require to use platform_set_drvdata() first in the ->probe
method?

> +
> +	clk_disable_unprepare(phy->cfg_clk);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id qcom_apq8064_sata_phy_of_match[] = {
> +	{ .compatible = "qcom,apq8064-sata-phy" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, qcom_apq8064_sata_phy_of_match);
> +
> +static struct platform_driver qcom_apq8064_sata_phy_driver = {
> +	.probe	= qcom_apq8064_sata_phy_probe,
> +	.remove	= qcom_apq8064_sata_phy_remove,
> +	.driver = {
> +		.name	= "qcom-apq8064-sata-phy",
> +		.owner	= THIS_MODULE,
> +		.of_match_table	= qcom_apq8064_sata_phy_of_match,
> +	}
> +};
> +module_platform_driver(qcom_apq8064_sata_phy_driver);
> +
> +MODULE_DESCRIPTION("QCOM apq8064 SATA PHY driver");
> +MODULE_LICENSE("GPL v2");

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Re: [PATCH v2 1/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Srinivas Kandagatla]

Thankyou for the comments,

On 11/07/14 13:38, Bartlomiej Zolnierkiewicz wrote:
>
> Hi,
>
> On Wednesday, July 09, 2014 12:04:06 PM Srinivas Kandagatla wrote:
>> Add a PHY driver for uses with AHCI based SATA controller driver on the
>> APQ8064 family of SoCs.
>>
>> This patch is a forward port from Qualcomm's v3.4 andriod kernel.
>
> Android?
yep.
>
> unused define, please remove it
>
Will fix these instances in next version.
>> +
>> +#define UNIPHY_PLL_LOCK		BIT(0)
>> +#define SATA_PHY_TX_CAL		BIT(0)
>> +#define SATA_PHY_RX_CAL		BIT(0)
>> +
>> +/* default timeout set to 1 sec */
>> +#define TIMEOUT_MS		10000
>> +
>> +struct qcom_apq8064_sata_phy {
>> +	void __iomem *mmio;
>> +	struct clk *cfg_clk;
>> +	struct device *dev;
>> +};
>> +
>> +/* Helper function to do poll and timeout */
>> +static int read_poll_timeout(void __iomem *addr, u32 mask)
>> +{
>> +	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
>> +	u32 val;
>> +
>> +	do {
>> +		cpu_relax();
>> +		val = readl_relaxed(addr);
>> +		if (val & mask)
>> +			break;
>> +	} while (!time_after(jiffies, timeout));
>
> It would be better to use usleep_[range]() (or even msleep() if needed)
> instead of just using cpu_relax().

We really want to poll the register here, usleep/msleep would be useful 
if we know already know how much delay is required, but in this case the 
its not true.

>> +
>> +static int qcom_apq8064_sata_phy_remove(struct platform_device *pdev)
>> +{
>> +	struct qcom_apq8064_sata_phy *phy = platform_get_drvdata(pdev);
>
> Doesn't this require to use platform_set_drvdata() first in the ->probe
> method?
Good spot, I will fix this in next version.

Thanks,
srini

Re: [PATCH v2 1/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Bartlomiej Zolnierkiewicz]

On Friday, July 11, 2014 02:39:05 PM Srinivas Kandagatla wrote:
> Thankyou for the comments,
> 
> On 11/07/14 13:38, Bartlomiej Zolnierkiewicz wrote:
> >
> > Hi,
> >
> > On Wednesday, July 09, 2014 12:04:06 PM Srinivas Kandagatla wrote:
> >> Add a PHY driver for uses with AHCI based SATA controller driver on the
> >> APQ8064 family of SoCs.
> >>
> >> This patch is a forward port from Qualcomm's v3.4 andriod kernel.
> >
> > Android?
> yep.
> >
> > unused define, please remove it
> >
> Will fix these instances in next version.
> >> +
> >> +#define UNIPHY_PLL_LOCK		BIT(0)
> >> +#define SATA_PHY_TX_CAL		BIT(0)
> >> +#define SATA_PHY_RX_CAL		BIT(0)
> >> +
> >> +/* default timeout set to 1 sec */
> >> +#define TIMEOUT_MS		10000
> >> +
> >> +struct qcom_apq8064_sata_phy {
> >> +	void __iomem *mmio;
> >> +	struct clk *cfg_clk;
> >> +	struct device *dev;
> >> +};
> >> +
> >> +/* Helper function to do poll and timeout */
> >> +static int read_poll_timeout(void __iomem *addr, u32 mask)
> >> +{
> >> +	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
> >> +	u32 val;
> >> +
> >> +	do {
> >> +		cpu_relax();
> >> +		val = readl_relaxed(addr);
> >> +		if (val & mask)
> >> +			break;
> >> +	} while (!time_after(jiffies, timeout));
> >
> > It would be better to use usleep_[range]() (or even msleep() if needed)
> > instead of just using cpu_relax().
> 
> We really want to poll the register here, usleep/msleep would be useful 
> if we know already know how much delay is required, but in this case the 
> its not true.

I don't mean replacing the whole function, you can still do polling with
i.e. doing usleep_range(1000, 2000) with 1000 retries.  The advantage of
doing it this way would be that processor could do some useful work or
sleep during wait time instead of just busy waiting.

One example of many how to do it:

drivers/i2c/busses/i2c-s3c2410.c:

static bool is_ack(struct s3c24xx_i2c *i2c)
{
        int tries;

        for (tries = 50; tries; --tries) {
                if (readl(i2c->regs + S3C2410_IICCON)
                        & S3C2410_IICCON_IRQPEND) {
                        if (!(readl(i2c->regs + S3C2410_IICSTAT)
                                & S3C2410_IICSTAT_LASTBIT))
                                return true;
                }
                usleep_range(1000, 2000);
        }
        dev_err(i2c->dev, "ack was not recieved\n");
        return false;
}

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Re: [PATCH v2 1/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Srinivas Kandagatla]

Thanks Bartlomiej for the advice,

I will give it a try and see.

On 11/07/14 15:33, Bartlomiej Zolnierkiewicz wrote:
>>>> struct qcom_apq8064_sata_phy {
>>>> > >>+	void __iomem *mmio;
>>>> > >>+	struct clk *cfg_clk;
>>>> > >>+	struct device *dev;
>>>> > >>+};
>>>> > >>+
>>>> > >>+/* Helper function to do poll and timeout */
>>>> > >>+static int read_poll_timeout(void __iomem *addr, u32 mask)
>>>> > >>+{
>>>> > >>+	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
>>>> > >>+	u32 val;
>>>> > >>+
>>>> > >>+	do {
>>>> > >>+		cpu_relax();
>>>> > >>+		val = readl_relaxed(addr);
>>>> > >>+		if (val & mask)
>>>> > >>+			break;
>>>> > >>+	} while (!time_after(jiffies, timeout));
>>> > >
>>> > >It would be better to use usleep_[range]() (or even msleep() if needed)
>>> > >instead of just using cpu_relax().
>> >
>> >We really want to poll the register here, usleep/msleep would be useful
>> >if we know already know how much delay is required, but in this case the
>> >its not true.
> I don't mean replacing the whole function, you can still do polling with
> i.e. doing usleep_range(1000, 2000) with 1000 retries.  The advantage of
> doing it this way would be that processor could do some useful work or
> sleep during wait time instead of just busy waiting.
>
> One example of many how to do it:
>
> drivers/i2c/busses/i2c-s3c2410.c:
>
> static bool is_ack(struct s3c24xx_i2c *i2c)
> {
>          int tries;
>
>          for (tries = 50; tries; --tries) {
>                  if (readl(i2c->regs + S3C2410_IICCON)
>                          & S3C2410_IICCON_IRQPEND) {
>                          if (!(readl(i2c->regs + S3C2410_IICSTAT)
>                                  & S3C2410_IICSTAT_LASTBIT))
>                                  return true;
>                  }
>                  usleep_range(1000, 2000);
>          }
>          dev_err(i2c->dev, "ack was not recieved\n");
>          return false;
> }


thanks,
srini

[PATCH v3 0/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Srinivas Kandagatla]

Hi Kishon,

First patch in this series adds support to the APQ8064 SATA PHY.
Second patch updates the existing Kumar gala's device tree PHY bindings
with APQ8064 soc specific compatible.

Eventhough there are two seperate drivers for both IPQ and APQ SOCs,
the bindings are exactly same, so I did not create new bindings document.

Could you please pick these patches for v3.17.

Changes since v2:
	- added usleep_range in poll timeout as discussed
		with Bartlomiej Zolnierkiewicz.
	- Added missing pdev_set_drvdata spotted by 
		Bartlomiej Zolnierkiewicz

Changes since v1:
	- included DT bindings in the series.

Thanks,
srini

Srinivas Kandagatla (2):
  phy: qcom: Add driver for QCOM APQ8064 SATA PHY
  phy: qcom: Update APQ8064 PHY device tree bindings

 Documentation/devicetree/bindings/phy/qcom-phy.txt |   3 +-
 drivers/phy/Kconfig                                |   7 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-qcom-apq8064-sata.c                | 288 +++++++++++++++++++++
 4 files changed, 298 insertions(+), 1 deletion(-)
 create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c

-- 
1.9.1

[PATCH v3 1/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Srinivas Kandagatla]

Add a PHY driver for uses with AHCI based SATA controller driver on the
APQ8064 family of SoCs.

This patch is a forward port from Qualcomm's v3.4 andriod kernel.

Tested on IFC6410 board.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 drivers/phy/Kconfig                 |   7 +
 drivers/phy/Makefile                |   1 +
 drivers/phy/phy-qcom-apq8064-sata.c | 288 ++++++++++++++++++++++++++++++++++++
 3 files changed, 296 insertions(+)
 create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index b7b6bce..39083c7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,6 +178,13 @@ config PHY_XGENE
 	help
 	  This option enables support for APM X-Gene SoC multi-purpose PHY.
 
+config PHY_QCOM_APQ8064_SATA
+	tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
+	depends on ARCH_QCOM
+	depends on HAS_IOMEM
+	depends on OF
+	select GENERIC_PHY
+
 config PHY_QCOM_IPQ806X_SATA
 	tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
 	depends on ARCH_QCOM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d950317..8782088 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,4 +20,5 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-apq8064-sata.c b/drivers/phy/phy-qcom-apq8064-sata.c
new file mode 100644
index 0000000..c9b4dd6
--- /dev/null
+++ b/drivers/phy/phy-qcom-apq8064-sata.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+
+/* PHY registers */
+#define UNIPHY_PLL_REFCLK_CFG		0x000
+#define UNIPHY_PLL_PWRGEN_CFG		0x014
+#define UNIPHY_PLL_GLB_CFG		0x020
+#define UNIPHY_PLL_SDM_CFG0		0x038
+#define UNIPHY_PLL_SDM_CFG1		0x03C
+#define UNIPHY_PLL_SDM_CFG2		0x040
+#define UNIPHY_PLL_SDM_CFG3		0x044
+#define UNIPHY_PLL_SDM_CFG4		0x048
+#define UNIPHY_PLL_SSC_CFG0		0x04C
+#define UNIPHY_PLL_SSC_CFG1		0x050
+#define UNIPHY_PLL_SSC_CFG2		0x054
+#define UNIPHY_PLL_SSC_CFG3		0x058
+#define UNIPHY_PLL_LKDET_CFG0		0x05C
+#define UNIPHY_PLL_LKDET_CFG1		0x060
+#define UNIPHY_PLL_LKDET_CFG2		0x064
+#define UNIPHY_PLL_CAL_CFG0		0x06C
+#define UNIPHY_PLL_CAL_CFG8		0x08C
+#define UNIPHY_PLL_CAL_CFG9		0x090
+#define UNIPHY_PLL_CAL_CFG10		0x094
+#define UNIPHY_PLL_CAL_CFG11		0x098
+#define UNIPHY_PLL_STATUS		0x0C0
+
+#define SATA_PHY_SER_CTRL		0x100
+#define SATA_PHY_TX_DRIV_CTRL0		0x104
+#define SATA_PHY_TX_DRIV_CTRL1		0x108
+#define SATA_PHY_TX_IMCAL0		0x11C
+#define SATA_PHY_TX_IMCAL2		0x124
+#define SATA_PHY_RX_IMCAL0		0x128
+#define SATA_PHY_EQUAL			0x13C
+#define SATA_PHY_OOB_TERM		0x144
+#define SATA_PHY_CDR_CTRL0		0x148
+#define SATA_PHY_CDR_CTRL1		0x14C
+#define SATA_PHY_CDR_CTRL2		0x150
+#define SATA_PHY_CDR_CTRL3		0x154
+#define SATA_PHY_PI_CTRL0		0x168
+#define SATA_PHY_POW_DWN_CTRL0		0x180
+#define SATA_PHY_POW_DWN_CTRL1		0x184
+#define SATA_PHY_TX_DATA_CTRL		0x188
+#define SATA_PHY_ALIGNP			0x1A4
+#define SATA_PHY_TX_IMCAL_STAT		0x1E4
+#define SATA_PHY_RX_IMCAL_STAT		0x1E8
+
+#define UNIPHY_PLL_LOCK		BIT(0)
+#define SATA_PHY_TX_CAL		BIT(0)
+#define SATA_PHY_RX_CAL		BIT(0)
+
+/* default timeout set to 1 sec */
+#define TIMEOUT_MS		10000
+#define DELAY_INTERVAL_US	100
+
+struct qcom_apq8064_sata_phy {
+	void __iomem *mmio;
+	struct clk *cfg_clk;
+	struct device *dev;
+};
+
+/* Helper function to do poll and timeout */
+static int read_poll_timeout(void __iomem *addr, u32 mask)
+{
+	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
+
+	do {
+		if (readl_relaxed(addr) & mask)
+			return 0;
+
+		 usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
+	} while (!time_after(jiffies, timeout));
+
+	return -ETIMEDOUT;
+}
+
+static int qcom_apq8064_sata_phy_init(struct phy *generic_phy)
+{
+	struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
+	void __iomem *base = phy->mmio;
+	int ret = 0;
+
+	/* SATA phy initialization */
+	writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
+	writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
+	/* Make sure the power down happens before power up */
+	mb();
+	usleep_range(10, 60);
+
+	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
+	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
+	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
+	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
+	writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
+
+	/* Write UNIPHYPLL registers to configure PLL */
+	writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
+	writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG);
+
+	writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0);
+	writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8);
+	writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9);
+	writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10);
+	writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11);
+
+	writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0);
+	writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1);
+	writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2);
+	writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3);
+	writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4);
+
+	writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0);
+	writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1);
+	writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2);
+	writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3);
+
+	writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0);
+	writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1);
+
+	writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG);
+	/* make sure global config LDO power down happens before power up */
+	mb();
+
+	writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG);
+	writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2);
+
+	/* PLL Lock wait */
+	ret = read_poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK);
+	if (ret) {
+		dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n");
+		return ret;
+	}
+
+	/* TX Calibration */
+	ret = read_poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL);
+	if (ret) {
+		dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n");
+		return ret;
+	}
+
+	/* RX Calibration */
+	ret = read_poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL);
+	if (ret) {
+		dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n");
+		return ret;
+	}
+
+	/* SATA phy calibrated succesfully, power up to functional mode */
+	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
+	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
+	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
+
+	writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1);
+	writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0);
+	writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1);
+	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2);
+	writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0);
+	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3);
+	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
+
+	writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL);
+	writel_relaxed(0x43, base + SATA_PHY_ALIGNP);
+	writel_relaxed(0x04, base + SATA_PHY_OOB_TERM);
+
+	writel_relaxed(0x01, base + SATA_PHY_EQUAL);
+	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0);
+	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1);
+
+	return 0;
+}
+
+static int qcom_apq8064_sata_phy_exit(struct phy *generic_phy)
+{
+	struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
+	void __iomem *base = phy->mmio;
+
+	/* Power down PHY */
+	writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0);
+	writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1);
+
+	/* Power down PLL block */
+	writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG);
+
+	return 0;
+}
+
+static struct phy_ops qcom_apq8064_sata_phy_ops = {
+	.init		= qcom_apq8064_sata_phy_init,
+	.exit		= qcom_apq8064_sata_phy_exit,
+	.owner		= THIS_MODULE,
+};
+
+static int qcom_apq8064_sata_phy_probe(struct platform_device *pdev)
+{
+	struct qcom_apq8064_sata_phy *phy;
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct phy_provider *phy_provider;
+	struct phy *generic_phy;
+	int ret;
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	phy->mmio = devm_ioremap_resource(dev, res);
+	if (IS_ERR(phy->mmio))
+		return PTR_ERR(phy->mmio);
+
+	generic_phy = devm_phy_create(dev, &qcom_apq8064_sata_phy_ops, NULL);
+	if (IS_ERR(generic_phy)) {
+		dev_err(dev, "%s: failed to create phy\n", __func__);
+		return PTR_ERR(generic_phy);
+	}
+
+	phy->dev = dev;
+	phy_set_drvdata(generic_phy, phy);
+	platform_set_drvdata(pdev, phy);
+
+	phy->cfg_clk = devm_clk_get(dev, "cfg");
+	if (IS_ERR(phy->cfg_clk)) {
+		dev_err(dev, "Failed to get sata cfg clock\n");
+		return PTR_ERR(phy->cfg_clk);
+	}
+
+	ret = clk_prepare_enable(phy->cfg_clk);
+	if (ret)
+		return ret;
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(phy_provider)) {
+		clk_disable_unprepare(phy->cfg_clk);
+		dev_err(dev, "%s: failed to register phy\n", __func__);
+		return PTR_ERR(phy_provider);
+	}
+
+	return 0;
+}
+
+static int qcom_apq8064_sata_phy_remove(struct platform_device *pdev)
+{
+	struct qcom_apq8064_sata_phy *phy = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(phy->cfg_clk);
+
+	return 0;
+}
+
+static const struct of_device_id qcom_apq8064_sata_phy_of_match[] = {
+	{ .compatible = "qcom,apq8064-sata-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, qcom_apq8064_sata_phy_of_match);
+
+static struct platform_driver qcom_apq8064_sata_phy_driver = {
+	.probe	= qcom_apq8064_sata_phy_probe,
+	.remove	= qcom_apq8064_sata_phy_remove,
+	.driver = {
+		.name	= "qcom-apq8064-sata-phy",
+		.owner	= THIS_MODULE,
+		.of_match_table	= qcom_apq8064_sata_phy_of_match,
+	}
+};
+module_platform_driver(qcom_apq8064_sata_phy_driver);
+
+MODULE_DESCRIPTION("QCOM apq8064 SATA PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

[PATCH v3 2/2] phy: qcom: Update APQ8064 PHY device tree bindings

[Srinivas Kandagatla]

Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on
the APQ8064 family of SoCs

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 Documentation/devicetree/bindings/phy/qcom-phy.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/qcom-phy.txt b/Documentation/devicetree/bindings/phy/qcom-phy.txt
index 76bfbd0..6bff1e0 100644
--- a/Documentation/devicetree/bindings/phy/qcom-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-phy.txt
@@ -1,4 +1,4 @@
-Qualcomm IPQ806x SATA PHY Controller
+Qualcomm IPQ806x/APQ8064 SATA PHY Controller
 ------------------------------------
 
 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
@@ -6,6 +6,7 @@ Each SATA PHY controller should have its own node.
 
 Required properties:
 - compatible: compatible list, contains "qcom,ipq806x-sata-phy"
+	     or "qcom,apq8064-sata-phy".
 - reg: offset and length of the SATA PHY register set;
 - #phy-cells: must be zero
 - clocks: must be exactly one entry
-- 
1.9.1

Re: [PATCH v3 0/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Kishon Vijay Abraham I]

On Monday 14 July 2014 02:17 PM, Srinivas Kandagatla wrote:
> Hi Kishon,
> 
> First patch in this series adds support to the APQ8064 SATA PHY.
> Second patch updates the existing Kumar gala's device tree PHY bindings
> with APQ8064 soc specific compatible.
> 
> Eventhough there are two seperate drivers for both IPQ and APQ SOCs,
> the bindings are exactly same, so I did not create new bindings document.

Er.. create a separate binding.
> 
> Could you please pick these patches for v3.17.

Sure. please rebase to linux-phy next and re-send.

Thanks
Kishon
> 
> Changes since v2:
> 	- added usleep_range in poll timeout as discussed
> 		with Bartlomiej Zolnierkiewicz.
> 	- Added missing pdev_set_drvdata spotted by 
> 		Bartlomiej Zolnierkiewicz
> 
> Changes since v1:
> 	- included DT bindings in the series.
> 
> Thanks,
> srini
> 
> Srinivas Kandagatla (2):
>   phy: qcom: Add driver for QCOM APQ8064 SATA PHY
>   phy: qcom: Update APQ8064 PHY device tree bindings
> 
>  Documentation/devicetree/bindings/phy/qcom-phy.txt |   3 +-
>  drivers/phy/Kconfig                                |   7 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-qcom-apq8064-sata.c                | 288 +++++++++++++++++++++
>  4 files changed, 298 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c
> 

Re: [PATCH v3 0/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Srinivas Kandagatla]

On 14/07/14 11:30, Kishon Vijay Abraham I wrote:
>
>
> On Monday 14 July 2014 02:17 PM, Srinivas Kandagatla wrote:
>> Hi Kishon,
>>
>> First patch in this series adds support to the APQ8064 SATA PHY.
>> Second patch updates the existing Kumar gala's device tree PHY bindings
>> with APQ8064 soc specific compatible.
>>
>> Eventhough there are two seperate drivers for both IPQ and APQ SOCs,
>> the bindings are exactly same, so I did not create new bindings document.
>
> Er.. create a separate binding.

Ok, no issues.
>>
>> Could you please pick these patches for v3.17.
>
> Sure. please rebase to linux-phy next and re-send.
I will do it.

thanks,
srini
>
> Thanks
> Kishon
>>
>> Changes since v2:
>> 	- added usleep_range in poll timeout as discussed
>> 		with Bartlomiej Zolnierkiewicz.
>> 	- Added missing pdev_set_drvdata spotted by
>> 		Bartlomiej Zolnierkiewicz
>>
>> Changes since v1:
>> 	- included DT bindings in the series.
>>
>> Thanks,
>> srini
>>
>> Srinivas Kandagatla (2):
>>    phy: qcom: Add driver for QCOM APQ8064 SATA PHY
>>    phy: qcom: Update APQ8064 PHY device tree bindings
>>
>>   Documentation/devicetree/bindings/phy/qcom-phy.txt |   3 +-
>>   drivers/phy/Kconfig                                |   7 +
>>   drivers/phy/Makefile                               |   1 +
>>   drivers/phy/phy-qcom-apq8064-sata.c                | 288 +++++++++++++++++++++
>>   4 files changed, 298 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c
>>

Re: [PATCH] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[kiran padwal]

tested-by: kiran.padwal@smartplayin.com

On Mon, Jun 23, 2014 at 11:30 PM, Srinivas Kandagatla
<srinivas.kandagatla@linaro.org> wrote:
> Add a PHY driver for uses with AHCI based SATA controller driver on the
> APQ8064 family of SoCs.
>
> This patch is a forward port plus separating PHY code of SATA driver
> from Qualcomm's v3.4 andriod kernel.
>
> Tested on IFC6410 board.
>
> CC: Sujit Reddy Thumma <sthumma@codeaurora.org>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> ---
>  drivers/phy/Kconfig                 |   7 +
>  drivers/phy/Makefile                |   1 +
>  drivers/phy/phy-qcom-apq8064-sata.c | 358 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 366 insertions(+)
>  create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index b7b6bce..39083c7 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -178,6 +178,13 @@ config PHY_XGENE
>         help
>           This option enables support for APM X-Gene SoC multi-purpose PHY.
>
> +config PHY_QCOM_APQ8064_SATA
> +       tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
> +       depends on ARCH_QCOM
> +       depends on HAS_IOMEM
> +       depends on OF
> +       select GENERIC_PHY
> +
>  config PHY_QCOM_IPQ806X_SATA
>         tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
>         depends on ARCH_QCOM
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index d950317..8782088 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -20,4 +20,5 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
>  phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)  += phy-exynos5250-usb2.o
>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)       += phy-exynos5-usbdrd.o
>  obj-$(CONFIG_PHY_XGENE)                        += phy-xgene.o
> +obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)    += phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)    += phy-qcom-ipq806x-sata.o
> diff --git a/drivers/phy/phy-qcom-apq8064-sata.c b/drivers/phy/phy-qcom-apq8064-sata.c
> new file mode 100644
> index 0000000..e9e59e2
> --- /dev/null
> +++ b/drivers/phy/phy-qcom-apq8064-sata.c
> @@ -0,0 +1,358 @@
> +/*
> + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/time.h>
> +#include <linux/delay.h>
> +#include <linux/clk.h>
> +#include <linux/slab.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +
> +/* PHY registers */
> +#define UNIPHY_PLL_REFCLK_CFG          0x000
> +#define UNIPHY_PLL_POSTDIV1_CFG                0x004
> +#define UNIPHY_PLL_CHGPUMP_CFG         0x008
> +#define UNIPHY_PLL_VCOLPF_CFG          0x00C
> +#define UNIPHY_PLL_VREG_CFG            0x010
> +#define UNIPHY_PLL_PWRGEN_CFG          0x014
> +#define UNIPHY_PLL_DMUX_CFG            0x018
> +#define UNIPHY_PLL_AMUX_CFG            0x01C
> +#define UNIPHY_PLL_GLB_CFG             0x020
> +#define UNIPHY_PLL_POSTDIV2_CFG                0x024
> +#define UNIPHY_PLL_POSTDIV3_CFG                0x028
> +#define UNIPHY_PLL_LPFR_CFG            0x02C
> +#define UNIPHY_PLL_LPFC1_CFG           0x030
> +#define UNIPHY_PLL_LPFC2_CFG           0x034
> +#define UNIPHY_PLL_SDM_CFG0            0x038
> +#define UNIPHY_PLL_SDM_CFG1            0x03C
> +#define UNIPHY_PLL_SDM_CFG2            0x040
> +#define UNIPHY_PLL_SDM_CFG3            0x044
> +#define UNIPHY_PLL_SDM_CFG4            0x048
> +#define UNIPHY_PLL_SSC_CFG0            0x04C
> +#define UNIPHY_PLL_SSC_CFG1            0x050
> +#define UNIPHY_PLL_SSC_CFG2            0x054
> +#define UNIPHY_PLL_SSC_CFG3            0x058
> +#define UNIPHY_PLL_LKDET_CFG0          0x05C
> +#define UNIPHY_PLL_LKDET_CFG1          0x060
> +#define UNIPHY_PLL_LKDET_CFG2          0x064
> +#define UNIPHY_PLL_TEST_CFG            0x068
> +#define UNIPHY_PLL_CAL_CFG0            0x06C
> +#define UNIPHY_PLL_CAL_CFG1            0x070
> +#define UNIPHY_PLL_CAL_CFG2            0x074
> +#define UNIPHY_PLL_CAL_CFG3            0x078
> +#define UNIPHY_PLL_CAL_CFG4            0x07C
> +#define UNIPHY_PLL_CAL_CFG5            0x080
> +#define UNIPHY_PLL_CAL_CFG6            0x084
> +#define UNIPHY_PLL_CAL_CFG7            0x088
> +#define UNIPHY_PLL_CAL_CFG8            0x08C
> +#define UNIPHY_PLL_CAL_CFG9            0x090
> +#define UNIPHY_PLL_CAL_CFG10           0x094
> +#define UNIPHY_PLL_CAL_CFG11           0x098
> +#define UNIPHY_PLL_EFUSE_CFG           0x09C
> +#define UNIPHY_PLL_DEBUG_BUS_SEL       0x0A0
> +#define UNIPHY_PLL_CTRL_42             0x0A4
> +#define UNIPHY_PLL_CTRL_43             0x0A8
> +#define UNIPHY_PLL_CTRL_44             0x0AC
> +#define UNIPHY_PLL_CTRL_45             0x0B0
> +#define UNIPHY_PLL_CTRL_46             0x0B4
> +#define UNIPHY_PLL_CTRL_47             0x0B8
> +#define UNIPHY_PLL_CTRL_48             0x0BC
> +#define UNIPHY_PLL_STATUS              0x0C0
> +#define UNIPHY_PLL_DEBUG_BUS0          0x0C4
> +#define UNIPHY_PLL_DEBUG_BUS1          0x0C8
> +#define UNIPHY_PLL_DEBUG_BUS2          0x0CC
> +#define UNIPHY_PLL_DEBUG_BUS3          0x0D0
> +#define UNIPHY_PLL_CTRL_54             0x0D4
> +
> +#define SATA_PHY_SER_CTRL              0x100
> +#define SATA_PHY_TX_DRIV_CTRL0         0x104
> +#define SATA_PHY_TX_DRIV_CTRL1         0x108
> +#define SATA_PHY_TX_DRIV_CTRL2         0x10C
> +#define SATA_PHY_TX_DRIV_CTRL3         0x110
> +#define SATA_PHY_TX_IMCAL0             0x11C
> +#define SATA_PHY_TX_IMCAL1             0x120
> +#define SATA_PHY_TX_IMCAL2             0x124
> +#define SATA_PHY_RX_IMCAL0             0x128
> +#define SATA_PHY_RX_IMCAL1             0x12C
> +#define SATA_PHY_RX_IMCAL2             0x130
> +#define SATA_PHY_RX_TERM               0x134
> +#define SATA_PHY_EQUAL                 0x13C
> +#define SATA_PHY_OOB_TERM              0x144
> +#define SATA_PHY_CDR_CTRL0             0x148
> +#define SATA_PHY_CDR_CTRL1             0x14C
> +#define SATA_PHY_CDR_CTRL2             0x150
> +#define SATA_PHY_CDR_CTRL3             0x154
> +#define SATA_PHY_CDR_CTRL4             0x158
> +#define SATA_PHY_FA_LOAD0              0x15C
> +#define SATA_PHY_FA_LOAD1              0x160
> +#define SATA_PHY_PI_CTRL0              0x168
> +#define SATA_PHY_PI_CTRL1              0x16C
> +#define SATA_PHY_AD_TPA_CTRL           0x178
> +#define SATA_PHY_REFCLK_CTRL           0x17C
> +#define SATA_PHY_POW_DWN_CTRL0         0x180
> +#define SATA_PHY_POW_DWN_CTRL1         0x184
> +#define SATA_PHY_TX_DATA_CTRL          0x188
> +#define SATA_PHY_BIST_GEN0             0x18C
> +#define SATA_PHY_BIST_GEN1             0x190
> +#define SATA_PHY_BIST_GEN2             0x194
> +#define SATA_PHY_BIST_GEN3             0x198
> +#define SATA_PHY_LBK_CTRL              0x19C
> +#define SATA_PHY_TEST_DEBUG_CTRL       0x1A0
> +#define SATA_PHY_ALIGNP                        0x1A4
> +#define SATA_PHY_PRBS_CFG0             0x1A8
> +#define SATA_PHY_PRBS_CFG1             0x1AC
> +#define SATA_PHY_PRBS_CFG2             0x1B0
> +#define SATA_PHY_PRBS_CFG3             0x1B4
> +#define SATA_PHY_CHAN_COMP_CHK_CNT     0x1B8
> +#define SATA_PHY_RESET_CTRL            0x1BC
> +#define SATA_PHY_RX_CLR                        0x1C0
> +#define SATA_PHY_RX_EBUF_CTRL          0x1C4
> +#define SATA_PHY_ID0                   0x1C8
> +#define SATA_PHY_ID1                   0x1CC
> +#define SATA_PHY_ID2                   0x1D0
> +#define SATA_PHY_ID3                   0x1D4
> +#define SATA_PHY_RX_CHK_ERR_CNT0       0x1D8
> +#define SATA_PHY_RX_CHK_ERR_CNT1       0x1DC
> +#define SATA_PHY_RX_CHK_STAT           0x1E0
> +#define SATA_PHY_TX_IMCAL_STAT         0x1E4
> +#define SATA_PHY_RX_IMCAL_STAT         0x1E8
> +#define SATA_PHY_RX_EBUF_STAT          0x1EC
> +#define SATA_PHY_DEBUG_BUS_STAT0       0x1F0
> +#define SATA_PHY_DEBUG_BUS_STAT1       0x1F4
> +#define SATA_PHY_DEBUG_BUS_STAT2       0x1F8
> +#define SATA_PHY_DEBUG_BUS_STAT3       0x1FC
> +
> +#define UNIPHY_PLL_LOCK                BIT(0)
> +#define SATA_PHY_TX_CAL                BIT(0)
> +#define SATA_PHY_RX_CAL                BIT(0)
> +
> +/* default timeout set to 1 sec */
> +#define TIMEOUT_MS             10000
> +
> +struct qcom_apq8064_sata_phy {
> +       void __iomem *mmio;
> +       struct clk *cfg_clk;
> +       struct device *dev;
> +};
> +
> +/* Helper function to do poll and timeout */
> +static int read_poll_timeout(void __iomem *addr, u32 mask)
> +{
> +       unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
> +       u32 val;
> +
> +       do {
> +               cpu_relax();
> +               val = readl_relaxed(addr);
> +               if (val & mask)
> +                       break;
> +       } while (!time_after(jiffies, timeout));
> +
> +       return (val & mask) ? 0 : -ETIMEDOUT;
> +}
> +
> +static int qcom_apq8064_sata_phy_init(struct phy *generic_phy)
> +{
> +       struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
> +       void __iomem *base = phy->mmio;
> +       int ret = 0;
> +
> +       /* SATA phy initialization */
> +       writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
> +       writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
> +       /* Make sure the power down happens before power up */
> +       mb();
> +       usleep_range(10, 60);
> +
> +       writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
> +       writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
> +       writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
> +       writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
> +       writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
> +
> +       /* Write UNIPHYPLL registers to configure PLL */
> +       writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
> +       writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG);
> +
> +       writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0);
> +       writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8);
> +       writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9);
> +       writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10);
> +       writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11);
> +
> +       writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0);
> +       writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1);
> +       writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2);
> +       writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3);
> +       writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4);
> +
> +       writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0);
> +       writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1);
> +       writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2);
> +       writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3);
> +
> +       writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0);
> +       writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1);
> +
> +       writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG);
> +       /* make sure global config LDO power down happens before power up */
> +       mb();
> +
> +       writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG);
> +       writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2);
> +
> +       /* PLL Lock wait */
> +       ret = read_poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK);
> +       if (ret) {
> +               dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n");
> +               return ret;
> +       }
> +
> +       /* TX Calibration */
> +       ret = read_poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL);
> +       if (ret) {
> +               dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n");
> +               return ret;
> +       }
> +
> +       /* RX Calibration */
> +       ret = read_poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL);
> +       if (ret) {
> +               dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n");
> +               return ret;
> +       }
> +
> +       /* SATA phy calibrated succesfully, power up to functional mode */
> +       writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
> +       writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
> +       writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
> +
> +       writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1);
> +       writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0);
> +       writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1);
> +       writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2);
> +       writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0);
> +       writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3);
> +       writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
> +
> +       writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL);
> +       writel_relaxed(0x43, base + SATA_PHY_ALIGNP);
> +       writel_relaxed(0x04, base + SATA_PHY_OOB_TERM);
> +
> +       writel_relaxed(0x01, base + SATA_PHY_EQUAL);
> +       writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0);
> +       writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1);
> +
> +       return 0;
> +}
> +
> +static int qcom_apq8064_sata_phy_exit(struct phy *generic_phy)
> +{
> +       struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
> +       void __iomem *base = phy->mmio;
> +
> +       /* Power down PHY */
> +       writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0);
> +       writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1);
> +
> +       /* Power down PLL block */
> +       writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG);
> +
> +       return 0;
> +}
> +
> +static struct phy_ops qcom_apq8064_sata_phy_ops = {
> +       .init           = qcom_apq8064_sata_phy_init,
> +       .exit           = qcom_apq8064_sata_phy_exit,
> +       .owner          = THIS_MODULE,
> +};
> +
> +static int qcom_apq8064_sata_phy_probe(struct platform_device *pdev)
> +{
> +       struct qcom_apq8064_sata_phy *phy;
> +       struct device *dev = &pdev->dev;
> +       struct resource *res;
> +       struct phy_provider *phy_provider;
> +       struct phy *generic_phy;
> +       int ret;
> +
> +       phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
> +       if (!phy)
> +               return -ENOMEM;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       phy->mmio = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(phy->mmio))
> +               return PTR_ERR(phy->mmio);
> +
> +       generic_phy = devm_phy_create(dev, &qcom_apq8064_sata_phy_ops, NULL);
> +       if (IS_ERR(generic_phy)) {
> +               dev_err(dev, "%s: failed to create phy\n", __func__);
> +               return PTR_ERR(generic_phy);
> +       }
> +
> +       phy->dev = dev;
> +       phy_set_drvdata(generic_phy, phy);
> +
> +       phy->cfg_clk = devm_clk_get(dev, "cfg");
> +       if (IS_ERR(phy->cfg_clk)) {
> +               dev_err(dev, "Failed to get sata cfg clock\n");
> +               return PTR_ERR(phy->cfg_clk);
> +       }
> +
> +       ret = clk_prepare_enable(phy->cfg_clk);
> +       if (ret)
> +               return ret;
> +
> +       phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +       if (IS_ERR(phy_provider)) {
> +               clk_disable_unprepare(phy->cfg_clk);
> +               dev_err(dev, "%s: failed to register phy\n", __func__);
> +               return PTR_ERR(phy_provider);
> +       }
> +
> +       return 0;
> +}
> +
> +static int qcom_apq8064_sata_phy_remove(struct platform_device *pdev)
> +{
> +       struct qcom_apq8064_sata_phy *phy = platform_get_drvdata(pdev);
> +
> +       clk_disable_unprepare(phy->cfg_clk);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id qcom_apq8064_sata_phy_of_match[] = {
> +       { .compatible = "qcom,apq8064-sata-phy" },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, qcom_apq8064_sata_phy_of_match);
> +
> +static struct platform_driver qcom_apq8064_sata_phy_driver = {
> +       .probe  = qcom_apq8064_sata_phy_probe,
> +       .remove = qcom_apq8064_sata_phy_remove,
> +       .driver = {
> +               .name   = "qcom-apq8064-sata-phy",
> +               .owner  = THIS_MODULE,
> +               .of_match_table = qcom_apq8064_sata_phy_of_match,
> +       }
> +};
> +module_platform_driver(qcom_apq8064_sata_phy_driver);
> +
> +MODULE_DESCRIPTION("QCOM apq8064 SATA PHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v4 0/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Srinivas Kandagatla]

Hi Kishon,

First patch in this series adds support to the APQ8064 SATA PHY.
Second patch updates the existing Kumar gala's device tree PHY bindings
with APQ8064 soc specific compatible.

Eventhough there are two seperate drivers for both IPQ and APQ SOCs,
the bindings are exactly same, so I did not create new bindings document.

Could you please pick these patches for v3.17.

Changes since v3:
	- Rebased to linux-phy next branch as requested by Kishon
	- Added dedicated apq8064 sata phy bindings as suggested by Kishon

Changes since v2:
	- added usleep_range in poll timeout as discussed
		with Bartlomiej Zolnierkiewicz.
	- Added missing pdev_set_drvdata spotted by 
		Bartlomiej Zolnierkiewicz

Changes since v1:
	- included DT bindings in the series.

Thanks,
srini

Srinivas Kandagatla (2):
  phy: qcom: Add driver for QCOM APQ8064 SATA PHY
  phy: qcom: Add APQ8064 SATA PHY device tree bindings

 .../bindings/phy/qcom-apq8064-sata-phy.txt         |  24 ++
 drivers/phy/Kconfig                                |   7 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-qcom-apq8064-sata.c                | 288 +++++++++++++++++++++
 4 files changed, 320 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt
 create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c

-- 
1.9.1

[PATCH v4 1/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Srinivas Kandagatla]

Add a PHY driver for uses with AHCI based SATA controller driver on the
APQ8064 family of SoCs.

This patch is a forward port from Qualcomm's v3.4 andriod kernel.

Tested on IFC6410 board.

CC: Sujit Reddy Thumma <sthumma@codeaurora.org>
Tested-by: Kiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 drivers/phy/Kconfig                 |   7 +
 drivers/phy/Makefile                |   1 +
 drivers/phy/phy-qcom-apq8064-sata.c | 288 ++++++++++++++++++++++++++++++++++++
 3 files changed, 296 insertions(+)
 create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5fceb33..e22b1d1 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -188,4 +188,11 @@ config PHY_XGENE
 	help
 	  This option enables support for APM X-Gene SoC multi-purpose PHY.
 
+config PHY_QCOM_APQ8064_SATA
+	tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
+	depends on ARCH_QCOM
+	depends on HAS_IOMEM
+	depends on OF
+	select GENERIC_PHY
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 54f04d0..a4819d3 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -21,3 +21,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
diff --git a/drivers/phy/phy-qcom-apq8064-sata.c b/drivers/phy/phy-qcom-apq8064-sata.c
new file mode 100644
index 0000000..c9b4dd6
--- /dev/null
+++ b/drivers/phy/phy-qcom-apq8064-sata.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+
+/* PHY registers */
+#define UNIPHY_PLL_REFCLK_CFG		0x000
+#define UNIPHY_PLL_PWRGEN_CFG		0x014
+#define UNIPHY_PLL_GLB_CFG		0x020
+#define UNIPHY_PLL_SDM_CFG0		0x038
+#define UNIPHY_PLL_SDM_CFG1		0x03C
+#define UNIPHY_PLL_SDM_CFG2		0x040
+#define UNIPHY_PLL_SDM_CFG3		0x044
+#define UNIPHY_PLL_SDM_CFG4		0x048
+#define UNIPHY_PLL_SSC_CFG0		0x04C
+#define UNIPHY_PLL_SSC_CFG1		0x050
+#define UNIPHY_PLL_SSC_CFG2		0x054
+#define UNIPHY_PLL_SSC_CFG3		0x058
+#define UNIPHY_PLL_LKDET_CFG0		0x05C
+#define UNIPHY_PLL_LKDET_CFG1		0x060
+#define UNIPHY_PLL_LKDET_CFG2		0x064
+#define UNIPHY_PLL_CAL_CFG0		0x06C
+#define UNIPHY_PLL_CAL_CFG8		0x08C
+#define UNIPHY_PLL_CAL_CFG9		0x090
+#define UNIPHY_PLL_CAL_CFG10		0x094
+#define UNIPHY_PLL_CAL_CFG11		0x098
+#define UNIPHY_PLL_STATUS		0x0C0
+
+#define SATA_PHY_SER_CTRL		0x100
+#define SATA_PHY_TX_DRIV_CTRL0		0x104
+#define SATA_PHY_TX_DRIV_CTRL1		0x108
+#define SATA_PHY_TX_IMCAL0		0x11C
+#define SATA_PHY_TX_IMCAL2		0x124
+#define SATA_PHY_RX_IMCAL0		0x128
+#define SATA_PHY_EQUAL			0x13C
+#define SATA_PHY_OOB_TERM		0x144
+#define SATA_PHY_CDR_CTRL0		0x148
+#define SATA_PHY_CDR_CTRL1		0x14C
+#define SATA_PHY_CDR_CTRL2		0x150
+#define SATA_PHY_CDR_CTRL3		0x154
+#define SATA_PHY_PI_CTRL0		0x168
+#define SATA_PHY_POW_DWN_CTRL0		0x180
+#define SATA_PHY_POW_DWN_CTRL1		0x184
+#define SATA_PHY_TX_DATA_CTRL		0x188
+#define SATA_PHY_ALIGNP			0x1A4
+#define SATA_PHY_TX_IMCAL_STAT		0x1E4
+#define SATA_PHY_RX_IMCAL_STAT		0x1E8
+
+#define UNIPHY_PLL_LOCK		BIT(0)
+#define SATA_PHY_TX_CAL		BIT(0)
+#define SATA_PHY_RX_CAL		BIT(0)
+
+/* default timeout set to 1 sec */
+#define TIMEOUT_MS		10000
+#define DELAY_INTERVAL_US	100
+
+struct qcom_apq8064_sata_phy {
+	void __iomem *mmio;
+	struct clk *cfg_clk;
+	struct device *dev;
+};
+
+/* Helper function to do poll and timeout */
+static int read_poll_timeout(void __iomem *addr, u32 mask)
+{
+	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
+
+	do {
+		if (readl_relaxed(addr) & mask)
+			return 0;
+
+		 usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
+	} while (!time_after(jiffies, timeout));
+
+	return -ETIMEDOUT;
+}
+
+static int qcom_apq8064_sata_phy_init(struct phy *generic_phy)
+{
+	struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
+	void __iomem *base = phy->mmio;
+	int ret = 0;
+
+	/* SATA phy initialization */
+	writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
+	writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
+	/* Make sure the power down happens before power up */
+	mb();
+	usleep_range(10, 60);
+
+	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
+	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
+	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
+	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
+	writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
+
+	/* Write UNIPHYPLL registers to configure PLL */
+	writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
+	writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG);
+
+	writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0);
+	writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8);
+	writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9);
+	writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10);
+	writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11);
+
+	writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0);
+	writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1);
+	writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2);
+	writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3);
+	writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4);
+
+	writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0);
+	writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1);
+	writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2);
+	writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3);
+
+	writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0);
+	writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1);
+
+	writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG);
+	/* make sure global config LDO power down happens before power up */
+	mb();
+
+	writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG);
+	writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2);
+
+	/* PLL Lock wait */
+	ret = read_poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK);
+	if (ret) {
+		dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n");
+		return ret;
+	}
+
+	/* TX Calibration */
+	ret = read_poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL);
+	if (ret) {
+		dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n");
+		return ret;
+	}
+
+	/* RX Calibration */
+	ret = read_poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL);
+	if (ret) {
+		dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n");
+		return ret;
+	}
+
+	/* SATA phy calibrated succesfully, power up to functional mode */
+	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
+	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
+	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
+
+	writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1);
+	writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0);
+	writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1);
+	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2);
+	writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0);
+	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3);
+	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
+
+	writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL);
+	writel_relaxed(0x43, base + SATA_PHY_ALIGNP);
+	writel_relaxed(0x04, base + SATA_PHY_OOB_TERM);
+
+	writel_relaxed(0x01, base + SATA_PHY_EQUAL);
+	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0);
+	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1);
+
+	return 0;
+}
+
+static int qcom_apq8064_sata_phy_exit(struct phy *generic_phy)
+{
+	struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
+	void __iomem *base = phy->mmio;
+
+	/* Power down PHY */
+	writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0);
+	writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1);
+
+	/* Power down PLL block */
+	writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG);
+
+	return 0;
+}
+
+static struct phy_ops qcom_apq8064_sata_phy_ops = {
+	.init		= qcom_apq8064_sata_phy_init,
+	.exit		= qcom_apq8064_sata_phy_exit,
+	.owner		= THIS_MODULE,
+};
+
+static int qcom_apq8064_sata_phy_probe(struct platform_device *pdev)
+{
+	struct qcom_apq8064_sata_phy *phy;
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct phy_provider *phy_provider;
+	struct phy *generic_phy;
+	int ret;
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	phy->mmio = devm_ioremap_resource(dev, res);
+	if (IS_ERR(phy->mmio))
+		return PTR_ERR(phy->mmio);
+
+	generic_phy = devm_phy_create(dev, &qcom_apq8064_sata_phy_ops, NULL);
+	if (IS_ERR(generic_phy)) {
+		dev_err(dev, "%s: failed to create phy\n", __func__);
+		return PTR_ERR(generic_phy);
+	}
+
+	phy->dev = dev;
+	phy_set_drvdata(generic_phy, phy);
+	platform_set_drvdata(pdev, phy);
+
+	phy->cfg_clk = devm_clk_get(dev, "cfg");
+	if (IS_ERR(phy->cfg_clk)) {
+		dev_err(dev, "Failed to get sata cfg clock\n");
+		return PTR_ERR(phy->cfg_clk);
+	}
+
+	ret = clk_prepare_enable(phy->cfg_clk);
+	if (ret)
+		return ret;
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(phy_provider)) {
+		clk_disable_unprepare(phy->cfg_clk);
+		dev_err(dev, "%s: failed to register phy\n", __func__);
+		return PTR_ERR(phy_provider);
+	}
+
+	return 0;
+}
+
+static int qcom_apq8064_sata_phy_remove(struct platform_device *pdev)
+{
+	struct qcom_apq8064_sata_phy *phy = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(phy->cfg_clk);
+
+	return 0;
+}
+
+static const struct of_device_id qcom_apq8064_sata_phy_of_match[] = {
+	{ .compatible = "qcom,apq8064-sata-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, qcom_apq8064_sata_phy_of_match);
+
+static struct platform_driver qcom_apq8064_sata_phy_driver = {
+	.probe	= qcom_apq8064_sata_phy_probe,
+	.remove	= qcom_apq8064_sata_phy_remove,
+	.driver = {
+		.name	= "qcom-apq8064-sata-phy",
+		.owner	= THIS_MODULE,
+		.of_match_table	= qcom_apq8064_sata_phy_of_match,
+	}
+};
+module_platform_driver(qcom_apq8064_sata_phy_driver);
+
+MODULE_DESCRIPTION("QCOM apq8064 SATA PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

[PATCH v4 2/2] phy: qcom: Add APQ8064 SATA PHY device tree bindings

[Srinivas Kandagatla]

This patch adds binding spec for Qualcomm AP8064 SATA PHY.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 .../bindings/phy/qcom-apq8064-sata-phy.txt         | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt b/Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt
new file mode 100644
index 0000000..952f6c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt
@@ -0,0 +1,24 @@
+Qualcomm APQ8064 SATA PHY Controller
+------------------------------------
+
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "qcom,apq8064-sata-phy".
+- reg: offset and length of the SATA PHY register set;
+- #phy-cells: must be zero
+- clocks: a list of phandles and clock-specifier pairs, one for each entry in
+  clock-names.
+- clock-names: must be "cfg" for phy config clock.
+
+Example:
+	sata_phy: sata-phy@1b400000 {
+		compatible = "qcom,apq8064-sata-phy";
+		reg = <0x1b400000 0x200>;
+
+		clocks = <&gcc SATA_PHY_CFG_CLK>;
+		clock-names = "cfg";
+
+		#phy-cells = <0>;
+	};
-- 
1.9.1

Re: [PATCH v4 1/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Bartlomiej Zolnierkiewicz]

Hi,

On Monday, July 14, 2014 12:17:59 PM Srinivas Kandagatla wrote:
> Add a PHY driver for uses with AHCI based SATA controller driver on the
> APQ8064 family of SoCs.
> 
> This patch is a forward port from Qualcomm's v3.4 andriod kernel.
> 
> Tested on IFC6410 board.
> 
> CC: Sujit Reddy Thumma <sthumma@codeaurora.org>
> Tested-by: Kiran Padwal <kiran.padwal@smartplayin.com>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> ---
>  drivers/phy/Kconfig                 |   7 +
>  drivers/phy/Makefile                |   1 +
>  drivers/phy/phy-qcom-apq8064-sata.c | 288 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 296 insertions(+)
>  create mode 100644 drivers/phy/phy-qcom-apq8064-sata.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 5fceb33..e22b1d1 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -188,4 +188,11 @@ config PHY_XGENE
>  	help
>  	  This option enables support for APM X-Gene SoC multi-purpose PHY.
>  
> +config PHY_QCOM_APQ8064_SATA
> +	tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
> +	depends on ARCH_QCOM
> +	depends on HAS_IOMEM
> +	depends on OF
> +	select GENERIC_PHY
> +
>  endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 54f04d0..a4819d3 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -21,3 +21,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o
>  phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>  obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o
> +obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
> diff --git a/drivers/phy/phy-qcom-apq8064-sata.c b/drivers/phy/phy-qcom-apq8064-sata.c
> new file mode 100644
> index 0000000..c9b4dd6
> --- /dev/null
> +++ b/drivers/phy/phy-qcom-apq8064-sata.c
> @@ -0,0 +1,288 @@
> +/*
> + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/time.h>
> +#include <linux/delay.h>
> +#include <linux/clk.h>
> +#include <linux/slab.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +
> +/* PHY registers */
> +#define UNIPHY_PLL_REFCLK_CFG		0x000
> +#define UNIPHY_PLL_PWRGEN_CFG		0x014
> +#define UNIPHY_PLL_GLB_CFG		0x020
> +#define UNIPHY_PLL_SDM_CFG0		0x038
> +#define UNIPHY_PLL_SDM_CFG1		0x03C
> +#define UNIPHY_PLL_SDM_CFG2		0x040
> +#define UNIPHY_PLL_SDM_CFG3		0x044
> +#define UNIPHY_PLL_SDM_CFG4		0x048
> +#define UNIPHY_PLL_SSC_CFG0		0x04C
> +#define UNIPHY_PLL_SSC_CFG1		0x050
> +#define UNIPHY_PLL_SSC_CFG2		0x054
> +#define UNIPHY_PLL_SSC_CFG3		0x058
> +#define UNIPHY_PLL_LKDET_CFG0		0x05C
> +#define UNIPHY_PLL_LKDET_CFG1		0x060
> +#define UNIPHY_PLL_LKDET_CFG2		0x064
> +#define UNIPHY_PLL_CAL_CFG0		0x06C
> +#define UNIPHY_PLL_CAL_CFG8		0x08C
> +#define UNIPHY_PLL_CAL_CFG9		0x090
> +#define UNIPHY_PLL_CAL_CFG10		0x094
> +#define UNIPHY_PLL_CAL_CFG11		0x098
> +#define UNIPHY_PLL_STATUS		0x0C0
> +
> +#define SATA_PHY_SER_CTRL		0x100
> +#define SATA_PHY_TX_DRIV_CTRL0		0x104
> +#define SATA_PHY_TX_DRIV_CTRL1		0x108
> +#define SATA_PHY_TX_IMCAL0		0x11C
> +#define SATA_PHY_TX_IMCAL2		0x124
> +#define SATA_PHY_RX_IMCAL0		0x128
> +#define SATA_PHY_EQUAL			0x13C
> +#define SATA_PHY_OOB_TERM		0x144
> +#define SATA_PHY_CDR_CTRL0		0x148
> +#define SATA_PHY_CDR_CTRL1		0x14C
> +#define SATA_PHY_CDR_CTRL2		0x150
> +#define SATA_PHY_CDR_CTRL3		0x154
> +#define SATA_PHY_PI_CTRL0		0x168
> +#define SATA_PHY_POW_DWN_CTRL0		0x180
> +#define SATA_PHY_POW_DWN_CTRL1		0x184
> +#define SATA_PHY_TX_DATA_CTRL		0x188
> +#define SATA_PHY_ALIGNP			0x1A4
> +#define SATA_PHY_TX_IMCAL_STAT		0x1E4
> +#define SATA_PHY_RX_IMCAL_STAT		0x1E8
> +
> +#define UNIPHY_PLL_LOCK		BIT(0)
> +#define SATA_PHY_TX_CAL		BIT(0)
> +#define SATA_PHY_RX_CAL		BIT(0)
> +
> +/* default timeout set to 1 sec */
> +#define TIMEOUT_MS		10000
> +#define DELAY_INTERVAL_US	100
> +
> +struct qcom_apq8064_sata_phy {
> +	void __iomem *mmio;
> +	struct clk *cfg_clk;
> +	struct device *dev;
> +};
> +
> +/* Helper function to do poll and timeout */
> +static int read_poll_timeout(void __iomem *addr, u32 mask)
> +{
> +	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
> +
> +	do {
> +		if (readl_relaxed(addr) & mask)
> +			return 0;
> +
> +		 usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
> +	} while (!time_after(jiffies, timeout));
> +
> +	return -ETIMEDOUT;
> +}

Thanks for reworking this code, unfortunately it still has a one
(unlikely but still theoretically possible) problem.  If there is
i.e. a big IRQ load between first usleep_range() call and first
time_after() check the function will timeout without checking
the register.  To fix it you needs to add an additonal register
checking before returning -ETIMEDOUT value or replace time_after()
condition with a fixed number of retries (100000 to cover 1sec
timeout).

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Re: [PATCH v4 1/2] phy: qcom: Add driver for QCOM APQ8064 SATA PHY

[Srinivas Kandagatla]

On 15/07/14 17:56, Bartlomiej Zolnierkiewicz wrote:
>> +
>> >+/* Helper function to do poll and timeout */
>> >+static int read_poll_timeout(void __iomem *addr, u32 mask)
>> >+{
>> >+	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
>> >+
>> >+	do {
>> >+		if (readl_relaxed(addr) & mask)
>> >+			return 0;
>> >+
>> >+		 usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
>> >+	} while (!time_after(jiffies, timeout));
>> >+
>> >+	return -ETIMEDOUT;
>> >+}
> Thanks for reworking this code, unfortunately it still has a one
> (unlikely but still theoretically possible) problem.  If there is
> i.e. a big IRQ load between first usleep_range() call and first

Very unlikely but as you said it possible in theory :-)

> time_after() check the function will timeout without checking
> the register.  To fix it you needs to add an additonal register
> checking before returning -ETIMEDOUT value or replace time_after()
> condition with a fixed number of retries (100000 to cover 1sec
> timeout).
I will send out a fix on top of my previous patches to fix this.

thanks,
srini