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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac23973810csm439279366b.118.2025.03.08.06.17.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 08 Mar 2025 06:17:29 -0800 (PST) Message-ID: <53c3d2c3-2bfb-43f9-ad25-0d1fdd96f19f@oss.qualcomm.com> Date: Sat, 8 Mar 2025 15:17:23 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/10] drm/msm/dsi/phy: add configuration for SAR2130P To: Dmitry Baryshkov , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Krishna Manikandan , Jonathan Marek , Bjorn Andersson , Neil Armstrong , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org References: <20250308-sar2130p-display-v1-0-1d4c30f43822@linaro.org> <20250308-sar2130p-display-v1-7-1d4c30f43822@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250308-sar2130p-display-v1-7-1d4c30f43822@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: vlqHgMo7O4pUjcusoWK24QbHhNrlCkhF X-Proofpoint-ORIG-GUID: vlqHgMo7O4pUjcusoWK24QbHhNrlCkhF X-Authority-Analysis: v=2.4 cv=ab+bnQot c=1 sm=1 tr=0 ts=67cc5184 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=KKAkSRfTAAAA:8 a=WWvJJprN3eueWNfT7O0A:9 a=QEXdDO2ut3YA:10 a=jpH7HpYVSZo6v3SV3j0F:22 a=iYH6xdkBrDN1Jqds4HTS:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-08_05,2025-03-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 bulkscore=0 mlxscore=0 impostorscore=0 phishscore=0 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503080107 On 8.03.2025 2:42 AM, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov > > Qualcomm SAR2130P requires slightly different setup for the DSI PHY. It > is a 5nm PHY (like SM8450), so supplies are the same, but the rest of > the configuration is the same as SM8550 DSI PHY. > > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +++++++++++++++++++++++ > 3 files changed, 26 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index c0bcc68289633fd7506ce4f1f963655d862e8f08..a58bafe9fe8635730cb82e8c82ec1ded394988cd 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -581,6 +581,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { > .data = &dsi_phy_7nm_cfgs }, > { .compatible = "qcom,dsi-phy-7nm-8150", > .data = &dsi_phy_7nm_8150_cfgs }, > + { .compatible = "qcom,sar2130p-dsi-phy-5nm", > + .data = &dsi_phy_5nm_sar2130p_cfgs }, > { .compatible = "qcom,sc7280-dsi-phy-7nm", > .data = &dsi_phy_7nm_7280_cfgs }, > { .compatible = "qcom,sm6375-dsi-phy-7nm", > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index 1925418d9999a24263d6621299cae78f1fb9455c..1ed08b56e056094bc0096d07d4470b89d9824060 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; > +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index a92decbee5b5433853ed973747f7705d9079068d..cad55702746b8d35949d22090796cca60f03b9e1 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -1289,6 +1289,29 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { > .quirks = DSI_PHY_7NM_QUIRK_V4_3, > }; > > +const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs = { > + .has_phy_lane = true, > + .regulator_data = dsi_phy_7nm_97800uA_regulators, > + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), > + .ops = { > + .enable = dsi_7nm_phy_enable, > + .disable = dsi_7nm_phy_disable, > + .pll_init = dsi_pll_7nm_init, > + .save_pll_state = dsi_7nm_pll_save_state, > + .restore_pll_state = dsi_7nm_pll_restore_state, > + .set_continuous_clock = dsi_7nm_set_continuous_clock, > + }, > + .min_pll_rate = 600000000UL, > +#ifdef CONFIG_64BIT > + .max_pll_rate = 5000000000UL, > +#else > + .max_pll_rate = ULONG_MAX, > +#endif > + .io_start = { 0xae95000, 0xae97000 }, > + .num_dsi_phy = 2, > + .quirks = DSI_PHY_7NM_QUIRK_V5_2, > +}; I'm squinting very very hard and can't tell how this is different from dsi_phy_4nm_8550_cfgs Konrad