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From: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
To: Jun Nie <jun.nie@linaro.org>
Cc: Rob Clark <robdclark@gmail.com>,
	Abhinav Kumar <quic_abhinavk@quicinc.com>,
	Dmitry Baryshkov <lumag@kernel.org>, Sean Paul <sean@poorly.run>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Jessica Zhang <quic_jesszhan@quicinc.com>,
	linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v15 00/13] drm/msm/dpu: Support quad pipe with dual-interface
Date: Tue, 2 Sep 2025 17:57:09 +0300	[thread overview]
Message-ID: <53z5v73r4ixmecpo6z3a6rnsmkgjjftbrwke24bf7mkr5ffh64@2viglv4lnows> (raw)
In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org>

On Tue, Aug 19, 2025 at 09:30:54AM +0800, Jun Nie wrote:
> 2 or more SSPPs and dual-DSI interface are need for super wide panel.
> And 4 DSC are preferred for power optimal in this case due to width
> limitation of SSPP and MDP clock rate constrain. This patch set
> extends number of pipes to 4 and revise related mixer blending logic
> to support quad pipe. All these changes depends on the virtual plane
> feature to split a super wide drm plane horizontally into 2 or more sub
> clip. Thus DMA of multiple SSPPs can share the effort of fetching the
> whole drm plane.
> 
> The first pipe pair co-work with the first mixer pair to cover the left
> half of screen and 2nd pair of pipes and mixers are for the right half
> of screen. If a plane is only for the right half of screen, only one
> or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is
> assinged for invalid pipe.
> 
> For those panel that does not require quad-pipe, only 1 or 2 pipes in
> the 1st pipe pair will be used. There is no concept of right half of
> screen.
> 
> For legacy non virtual plane mode, the first 1 or 2 pipes are used for
> the single SSPP and its multi-rect mode.
> 
> Changes in v15:
> - Polish logic in sspp check and assignment.
> - Link to v14: https://lore.kernel.org/r/20250801-v6-16-rc2-quad-pipe-upstream-v14-0-b626236f4c31@linaro.org

I tried picking up these patches into the msm-next-lumag, however they
seem to trigger a lot of IGT test failures. See [1]. Could you please
take a look at those failures? Note, virtual planes are still disabled
by default.

[1] https://gitlab.freedesktop.org/drm/msm/-/pipelines/1502582


-- 
With best wishes
Dmitry

      parent reply	other threads:[~2025-09-02 14:57 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-19  1:30 [PATCH v15 00/13] drm/msm/dpu: Support quad pipe with dual-interface Jun Nie
2025-08-19  1:30 ` [PATCH v15 01/13] drm/msm: Do not validate SSPP when it is not ready Jun Nie
2025-08-19  1:30 ` [PATCH v15 02/13] drm/msm/dpu: polish log for resource allocation Jun Nie
2025-08-19  1:30 ` [PATCH v15 03/13] drm/msm/dpu: decide right side per last bit Jun Nie
2025-08-19  1:30 ` [PATCH v15 04/13] drm/msm/dpu: fix mixer number counter on allocation Jun Nie
2025-08-19  1:30 ` [PATCH v15 05/13] drm/msm/dpu: bind correct pingpong for quad pipe Jun Nie
2025-08-19  1:31 ` [PATCH v15 06/13] drm/msm/dpu: Add pipe as trace argument Jun Nie
2025-08-19  1:31 ` [PATCH v15 07/13] drm/msm/dpu: handle pipes as array Jun Nie
2025-08-19  1:31 ` [PATCH v15 08/13] drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer Jun Nie
2025-08-19  1:31 ` [PATCH v15 09/13] drm/msm/dpu: Use dedicated WB number definition Jun Nie
2025-08-19  1:31 ` [PATCH v15 10/13] drm/msm/dpu: blend pipes per mixer pairs config Jun Nie
2025-08-19  1:31 ` [PATCH v15 11/13] drm/msm/dpu: support SSPP assignment for quad-pipe case Jun Nie
2025-08-19 19:01   ` Dmitry Baryshkov
2025-08-20 18:17   ` Jessica Zhang
2025-08-19  1:31 ` [PATCH v15 12/13] drm/msm/dpu: support plane splitting in " Jun Nie
2025-09-03  9:39   ` Dmitry Baryshkov
2025-08-19  1:31 ` [PATCH v15 13/13] drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case Jun Nie
2025-09-02 14:57 ` Dmitry Baryshkov [this message]

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