From: Stephen Boyd <sboyd@codeaurora.org>
To: Mike Turquette <mturquette@linaro.org>
Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Kumar Gala <galak@codeaurora.org>,
Andy Gross <agross@codeaurora.org>
Subject: Re: [PATCH] clk: qcom: Fix sdc 144kHz frequency entry
Date: Tue, 02 Sep 2014 15:01:15 -0700 [thread overview]
Message-ID: <54063E2B.6090403@codeaurora.org> (raw)
In-Reply-To: <20140902214402.5251.75274@quantum>
On 09/02/14 14:44, Mike Turquette wrote:
> Quoting Stephen Boyd (2014-08-29 12:49:26)
>> The pre-divider for the sdc clocks only has 2 bits in it, so we
>> can't possibly divide by anything larger than 4 here.
>> Furthermore, we program the value of ~(n - m) and the n value is
>> larger than 8 bits (max of 256). Replace this entry with 200kHz
>> which is close enough to 144kHz to be usable.
>>
>> Cc: Kumar Gala <galak@codeaurora.org>
>> Cc: Andy Gross <agross@codeaurora.org>
>> Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> Do you need this pulled into a 3.17-rc?
>
Yes that would be helpful since this fixes a driver introduced into 3.17.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
next prev parent reply other threads:[~2014-09-02 22:01 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-29 19:49 [PATCH] clk: qcom: Fix sdc 144kHz frequency entry Stephen Boyd
2014-09-02 21:44 ` Mike Turquette
2014-09-02 22:01 ` Stephen Boyd [this message]
2014-09-02 23:52 ` Mike Turquette
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