From mboxrd@z Thu Jan 1 00:00:00 1970 From: Archit Taneja Subject: Re: [PATCH v3 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines Date: Tue, 24 Mar 2015 10:17:58 +0530 Message-ID: <5510EC7E.5050900@codeaurora.org> References: <1426276174-17010-1-git-send-email-sviau@codeaurora.org> <1426276174-17010-4-git-send-email-sviau@codeaurora.org> <550FF006.6090600@codeaurora.org> <55c570957f9bac126093c9412e5797e9.squirrel@www.codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <55c570957f9bac126093c9412e5797e9.squirrel@www.codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: =?windows-1252?Q?St=E9phane_Viau?= Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, robdclark@gmail.com List-Id: linux-arm-msm@vger.kernel.org On 03/24/2015 03:40 AM, "St=E9phane Viau" wrote: > Hi Archit, > >> Hi Stephane, >> >> On 03/14/2015 01:19 AM, Stephane Viau wrote: >>> Some interfaces (WB, DSI Command Mode) need to be kicked off >>> through a START Signal. This signal needs to be sent at the right >>> time and requests in some cases to keep track of the pipeline >>> status (eg: whether pipeline registers are flushed AND output WB >>> buffers are ready, in case of WB interface). >>> >>> Signed-off-by: Stephane Viau >>> --- >>> drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 2 + >>> drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 7 +- >>> drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 31 ++-- >>> drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 247 >>> ++++++++++++++++++++++++---- >>> drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 72 +++----- >>> drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 13 +- >>> drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 + >>> 7 files changed, 276 insertions(+), 97 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c >>> b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c >>> index c078f30..72c075a 100644 >>> --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c >>> +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c >>> @@ -31,6 +31,7 @@ const struct mdp5_cfg_hw msm8x74_config =3D { >>> .ctl =3D { >>> .count =3D 5, >>> .base =3D { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, >>> + .flush_hw_mask =3D 0x0003ffff, >>> }, >>> .pipe_vig =3D { >>> .count =3D 3, >>> @@ -78,6 +79,7 @@ const struct mdp5_cfg_hw apq8084_config =3D { >>> .ctl =3D { >>> .count =3D 5, >>> .base =3D { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, >>> + .flush_hw_mask =3D 0x003fffff, >> >> msm8x16 would require a flush_hw_mask too, it should be 0x32a59 if I= 'm >> not wrong. Could you please add it for the next revision, or as a pa= rt >> of the 8x16 hw cfg patch? > > Correct; thanks for pointing this out. > > IMO, this value should be 0x4003ffff because the fields are actually > present in the register (even though the interfaces/pipes.etc. are no= t). > Anyway, these bits won't be accessed because the driver won't even al= low > the usage of the corresponding resources. > Okay, that makes sense. > I will update in the v2 of "drm/msm/mdp5: Add hardware configuration = for > msm8x16". > > Thanks, > Stephane. > Thanks! Archit --=20 Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project