From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stanimir Varbanov Subject: Re: [PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised Date: Wed, 2 Dec 2015 14:56:57 +0200 Message-ID: <565EEA99.3070207@linaro.org> References: <1448961299-15161-1-git-send-email-stanimir.varbanov@linaro.org> <1448961299-15161-3-git-send-email-stanimir.varbanov@linaro.org> <6461444.oollnBsbrb@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wm0-f52.google.com ([74.125.82.52]:38680 "EHLO mail-wm0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756512AbbLBM5H (ORCPT ); Wed, 2 Dec 2015 07:57:07 -0500 Received: by wmec201 with SMTP id c201so56681955wme.1 for ; Wed, 02 Dec 2015 04:57:05 -0800 (PST) In-Reply-To: <6461444.oollnBsbrb@wuerfel> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Arnd Bergmann , linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, Vinod Koul , Mark Rutland , Archit Taneja , Pawel Moll , Ian Campbell , Rob Herring , Andy Gross On 12/01/2015 12:29 PM, Arnd Bergmann wrote: > On Tuesday 01 December 2015 11:14:57 Stanimir Varbanov wrote: >> + if (srcs & BAM_IRQ) { >> clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); >> >> - /* don't allow reorder of the various accesses to the BAM registers */ >> - mb(); >> + /* >> + * don't allow reorder of the various accesses to the BAM >> + * registers >> + */ >> + mb(); >> >> - writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR)); >> + writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR)); >> + } >> > > I think the comment here should be moved: change the writel_relaxed() > to writel(), which already includes the appropriate barriers, and If we agree with such a change it should be subject to another patch. > add a comment at the readl_relaxed() to explain why it doesn't need > a barrier. Infact I'm not sure that readl_relaxed(BAM_IRQ_STTS) does not need barrier. If I read the code above correctly the mb() should guarantee that all load and store operations before it are happened before the write to BAM_IRQ_CLR register, and on the other hand if we replace writel_relaxed with writel, the writel has wmb() which guarantees only store operations. Did I miss something? -- regards, Stan