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Fri, 15 May 2020 10:56:07 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id B2DAAC432C2; Fri, 15 May 2020 10:56:06 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5E62DC433D2; Fri, 15 May 2020 10:55:59 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Fri, 15 May 2020 16:25:59 +0530 From: Sai Prakash Ranjan To: Mathieu Poirier , Suzuki K Poulose , Mike Leach , devicetree@vger.kernel.org, Rob Herring , Bjorn Andersson , Andy Gross Cc: Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org Subject: Re: [PATCH 1/2] arm64: dts: qcom: sc7180: Support ETMv4 power management In-Reply-To: References: Message-ID: <56a5563205da61c47eb4f8bbf6120e28@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Bjorn, On 2020-05-15 16:21, Sai Prakash Ranjan wrote: > Now that deep idle states are properly supported on SC7180, > we need to add "coresight-loses-context-with-cpu" property > to avoid failure of trace session because of losing context > on entering deep idle states. > > Reviewed-by: Stephen Boyd > Signed-off-by: Sai Prakash Ranjan > --- > > Resending this because the last patch sent here - > https://lore.kernel.org/patchwork/patch/1230367/ > seems to have added "coresight-loses-context-with-cpu" to > replicator node instead of etm7 node. > > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi > b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index 4069bb1c93af..8b3707347547 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -1656,6 +1656,7 @@ > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -1674,6 +1675,7 @@ > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -1692,6 +1694,7 @@ > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -1710,6 +1713,7 @@ > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -1728,6 +1732,7 @@ > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -1746,6 +1751,7 @@ > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -1764,6 +1770,7 @@ > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -1782,6 +1789,7 @@ > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { The previous version of this patch in QCOM tree seems to have added the property to replicator node instead of etm7 node, can you please drop that from the tree and apply this one? Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation