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Fri, 19 Dec 2025 02:39:27 -0800 (PST) X-Google-Smtp-Source: AGHT+IHHjjNmZyZL1M8MmrxLZpRtoEvO3hbj9TdfoS3U+i8ntekOrSW1gOPRLwiSGrbGBtNeQBc0kQ== X-Received: by 2002:a17:902:e884:b0:2a0:b467:a7ce with SMTP id d9443c01a7336-2a2f27352a7mr27092615ad.36.1766140766585; Fri, 19 Dec 2025 02:39:26 -0800 (PST) Received: from [10.217.217.147] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3c66472sm19494225ad.13.2025.12.19.02.39.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Dec 2025 02:39:26 -0800 (PST) Message-ID: <57ab2d5d-5aaa-4f9c-83ae-0f7ebc1e648b@oss.qualcomm.com> Date: Fri, 19 Dec 2025 16:09:18 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 07/11] dt-bindings: clock: qcom: document the Kaanapali GPU Clock Controller To: Krzysztof Kozlowski , Konrad Dybcio Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Maxime Coquelin , Alexandre Torgue , Vladimir Zapolskiy , Konrad Dybcio , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Jingyi Wang , Bryan O'Donoghue References: <20251125-kaanapali-mmcc-v2-v2-0-fb44e78f300b@oss.qualcomm.com> <20251125-kaanapali-mmcc-v2-v2-7-fb44e78f300b@oss.qualcomm.com> <20251126-elated-stoic-scorpion-25b630@kuoka> <503f445e-0d12-407d-bc77-f48ad335639b@oss.qualcomm.com> <3e8128f4-3cba-4c13-a846-e5f1638a1e0f@kernel.org> Content-Language: en-US From: Taniya Das In-Reply-To: <3e8128f4-3cba-4c13-a846-e5f1638a1e0f@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: p637w43JHZkCDKDyCki_Or83eIF-Ynh4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA4NyBTYWx0ZWRfX5AxENkaKxfhk SZ89yc1n7OkbWtFdJe+YW+ozKQXiNq3NO2+tr3+e0JWMgESH/6F9bdfagYz8oVOO5lfem2KZ4zv 48Llmr9hdrjuXSmmJ7cXN1hv2cQxED03FAwPIvE/PLCJnwSdMKGo6f06/PhDGF6PCpAEssCAWxi XDWuhUky/JVUqBinP4bQWp46xZHFi2PFYqdwoJVR7GXzVmOM6JHvQq0IvVLtaTccdNnbpp1XIFc BtRPMjPQonl6ylkQRgOKBqKdkY8Ly2SH7g7UuqrCpcYT7VG7auQ6Uun+xFYIVpjg49zfXRaz2s9 AO09WREhv50gEtOUX5IjB5xW08fRhmvco/VyQRzMwAa20P6X1jDukyiCogjPJAdDZyxPSnmN273 YXbWvKsbccen3M6lorScIDg5VqM9qp8hhtrtKKoohYiF2VVe2KTTCpW9ohMR1y/MICt0IJTPzj4 LiL7fjjWrugsTA33Ivg== X-Proofpoint-ORIG-GUID: p637w43JHZkCDKDyCki_Or83eIF-Ynh4 X-Authority-Analysis: v=2.4 cv=Lp2fC3dc c=1 sm=1 tr=0 ts=69452b5f cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=bZysObWQuULb7_ZgAGEA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_03,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190087 On 12/17/2025 7:24 PM, Krzysztof Kozlowski wrote: > On 17/12/2025 14:21, Konrad Dybcio wrote: >> On 12/17/25 11:09 AM, Krzysztof Kozlowski wrote: >>> On 17/12/2025 10:32, Taniya Das wrote: >>>>>> >>>>>> We would like to leverage the existing common clock driver(GDSC) code to >>>>> >>>>> Fix the driver code if it cannot handle other cells. Your drivers do not >>>>> matter for choices made in bindings. >>>>> >>>> >>>> As it is still a clock controller from hardware design and in SW I will >>>> be map the entire hardware region and this way this clock controller >>>> will also be aligned to the existing clock controllers and keep the >>>> #power-domain-cells = <1> as other CCs. >>> >>> I don't see how this resolves my comment. >> >> Spanning the entire 0x6000-long block will remove your worry about this >> description only being 2-register-wide > > But that was not the comment here. Taniya replied under comment about > cells. We are not discussing here some other things... > I will review and add support for handling #power-domain-cells = <0> in our common code of clock & gdsc. However, the initial intent was to keep the GDSC phandle uniform across chipsets as this is a clock controller by hardware design, which is why #power-domain-cells was originally set to <1>. -- Thanks, Taniya Das