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[192.35.156.11]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-747afff7e3bsm11752681b3a.175.2025.06.04.10.39.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Jun 2025 10:39:01 -0700 (PDT) Message-ID: <584d217a-e8df-4dbe-ad70-2c69597a0545@oss.qualcomm.com> Date: Wed, 4 Jun 2025 10:38:06 -0700 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex To: linux-pci@vger.kernel.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, andersson@kernel.org, manivannan.sadhasivam@linaro.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, quic_ramkri@quicinc.com, quic_nkela@quicinc.com, quic_shazhuss@quicinc.com, quic_msarkar@quicinc.com, quic_nitegupt@quicinc.com References: <20250522001425.1506240-1-mayank.rana@oss.qualcomm.com> Content-Language: en-US From: Mayank Rana In-Reply-To: <20250522001425.1506240-1-mayank.rana@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=RMizH5i+ c=1 sm=1 tr=0 ts=684084b7 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ZdW6uxA9NKXbfdqeeS2OGA==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=X0UA8UkCL550gklx81IA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjA0MDEzNyBTYWx0ZWRfX0Fq1ubRe1t8o LL+Rh7jV9SuYtSrNyF1roi6PDy0ncYsfg1KLpxCR2rAgmKuNRgo7r79CC/mcn3t4RMgi8OlGG7i 6kHyBXTpdE6Zk3cGfvtABCCibsdz3notIThcKOq/kOin+tWAiZNGj+XB3zKOip1TAOxRX7Aw4kt e5gWV2k/3khDM23fyq9d2OJ3SmOJpkMmZndhoKBbq9/l4N7pxVmyClDk4Z3OtkGc1al+Ow4dy3W 3BNZrN1Ik0uJCa6jci23SFKURAeMSIPHZZr3P6TiTcLo62ZEUJDX/c+PzdykwkqOCK/uOeW5T9U tYosrpNtIYd8wcSAnmoLaA6JkGpnLKeR0cxAvFDdeXDNNj1vtjn0lC8DVlRNLD+KWNp87c9z67q cBuhHInU4jcfCw2TmUgQBbxCTbQD24AgLDnrFz3B9GkYpoQMcONSzz7tS/YjGFy1pxPIAHOx X-Proofpoint-GUID: n0sl2-fZy53L_8I9kC9iAOpocaV6zfcq X-Proofpoint-ORIG-GUID: n0sl2-fZy53L_8I9kC9iAOpocaV6zfcq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-04_04,2025-06-03_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 suspectscore=0 adultscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506040137 Hi Mani As we discussed previously, I resumed working on this functionality. Please help with reviewing this patchset. Regards, Mayank On 5/21/2025 5:14 PM, Mayank Rana wrote: > Based on received feedback, this patch series adds support with existing > Linux qcom-pcie.c driver to get PCIe host root complex functionality on > Qualcomm SA8255P auto platform. > > 1. Interface to allow requesting firmware to manage system resources and > performing PCIe Link up (devicetree binding in terms of power domain and > runtime PM APIs is used in driver) > > 2. SA8255P is using Synopsys Designware PCIe controller which supports MSI > controller. Using existing MSI controller based functionality by exporting > important pcie dwc core driver based MSI APIs, and using those from > pcie-qcom.c driver. > > Below architecture is used on Qualcomm SA8255P auto platform to get ECAM > compliant PCIe controller based functionality. Here firmware VM based PCIe > driver takes care of resource management and performing PCIe link related > handling (D0 and D3cold). Linux pcie-qcom.c driver uses power domain to > request firmware VM to perform these operations using SCMI interface. > -------------------- > > > ┌────────────────────────┐ > │ │ > ┌──────────────────────┐ │ SHARED MEMORY │ ┌──────────────────────────┐ > │ Firmware VM │ │ │ │ Linux VM │ > │ ┌─────────┐ │ │ │ │ ┌────────────────┐ │ > │ │ Drivers │ ┌──────┐ │ │ │ │ │ PCIE Qcom │ │ > │ │ PCIE PHY◄─┤ │ │ │ ┌────────────────┐ │ │ │ driver │ │ > │ │ │ │ SCMI │ │ │ │ │ │ │ │ │ │ > │ │PCIE CTL │ │ │ ├─────────┼───► PCIE ◄───┼─────┐ │ └──┬──────────▲──┘ │ > │ │ ├─►Server│ │ │ │ SHMEM │ │ │ │ │ │ │ > │ │Clk, Vreg│ │ │ │ │ │ │ │ │ │ ┌──▼──────────┴──┐ │ > │ │GPIO,GDSC│ └─▲──┬─┘ │ │ └────────────────┘ │ └──────┼────┤PCIE SCMI Inst │ │ > │ └─────────┘ │ │ │ │ │ │ └──▲──────────┬──┘ │ > │ │ │ │ │ │ │ │ │ │ > └───────────────┼──┼───┘ │ │ └───────┼──────────┼───────┘ > │ │ │ │ │ │ > │ │ └────────────────────────┘ │ │ > │ │ │ │ > │ │ │ │ > │ │ │ │ > │ │ │IRQ │HVC > IRQ │ │HVC │ │ > │ │ │ │ > │ │ │ │ > │ │ │ │ > ┌─────────────────┴──▼───────────────────────────────────────────────────────────┴──────────▼──────────────┐ > │ │ > │ │ > │ HYPERVISOR │ > │ │ > │ │ > │ │ > └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ > > ┌─────────────┐ ┌─────────────┐ ┌──────────┐ ┌───────────┐ ┌─────────────┐ ┌────────────┐ > │ │ │ │ │ │ │ │ │ PCIE │ │ PCIE │ > │ CLOCK │ │ REGULATOR │ │ GPIO │ │ GDSC │ │ PHY │ │ controller │ > └─────────────┘ └─────────────┘ └──────────┘ └───────────┘ └─────────────┘ └────────────┘ > ----------------- > Changes in v4: > - Addressed provided review comments from reviewers > Link to v3: https://lore.kernel.org/lkml/20241106221341.2218416-1-quic_mrana@quicinc.com/ > > Changes in v3: > - Drop usage of PCIE host generic driver usage, and splitting of MSI functionality > - Modified existing pcie-qcom.c driver to add support for getting ECAM compliant and firmware managed > PCIe root complex functionality > Link to v2: https://lore.kernel.org/linux-arm-kernel/925d1eca-975f-4eec-bdf8-ca07a892361a@quicinc.com/T/ > > Changes in v2: > - Drop new PCIe Qcom ECAM driver, and use existing PCIe designware based MSI functionality > - Add power domain based functionality within existing ECAM driver > Link to v1: https://lore.kernel.org/all/d10199df-5fb3-407b-b404-a0a4d067341f@quicinc.com/T/ > > Tested: > - Validated NVME functionality with PCIe1 on SA8255P-RIDE platform > > Mayank Rana (4): > PCI: dwc: Export dwc MSI controller related APIs > PCI: host-generic: Rename and export gen_pci_init() API to allow ECAM > creation > dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root > complex > PCI: qcom: Add Qualcomm SA8255p based PCIe root complex functionality > > .../bindings/pci/qcom,pcie-sa8255p.yaml | 103 ++++++++++++++++ > drivers/pci/controller/dwc/Kconfig | 1 + > .../pci/controller/dwc/pcie-designware-host.c | 38 +++--- > drivers/pci/controller/dwc/pcie-designware.h | 14 +++ > drivers/pci/controller/dwc/pcie-qcom.c | 114 ++++++++++++++++-- > drivers/pci/controller/pci-host-common.c | 5 +- > include/linux/pci-ecam.h | 2 + > 7 files changed, 248 insertions(+), 29 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml >