Re: [PATCH v1 1/3] PCI: qcom: Setup PCIE20_PARF_BDF_TRANSLATE_N

[Stanimir Varbanov via iommu <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>]

Hi Marc,

Thank you for the work on that!

On 3/28/19 7:01 PM, Marc Gonzalez wrote:
> Initialize PCIE20_PARF_BDF_TRANSLATE_N for ops_2_3_2.
> 
> Signed-off-by: Marc Gonzalez <marc.w.gonzalez-GANU6spQydw@public.gmane.org>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 0ed235d560e3..5e5522a427b8 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -54,6 +54,7 @@
>  #define PCIE20_PARF_LTSSM			0x1B0
>  #define PCIE20_PARF_SID_OFFSET			0x234
>  #define PCIE20_PARF_BDF_TRANSLATE_CFG		0x24C
> +#define PCIE20_PARF_BDF_TRANSLATE_N		0x250
>  
>  #define PCIE20_ELBI_SYS_CTRL			0x04
>  #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE		BIT(0)
> @@ -602,6 +603,9 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
>  	val |= BIT(31);
>  	writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
>  
> +	val = PCI_DEVID(1, 0);
> +	writel(val, pcie->parf + PCIE20_PARF_BDF_TRANSLATE_N);

I wonder, shouldn't this register manipulation happen in common code
e.g. pcie-designware-host.c and of course the manipulation should be
conditional because not all platforms might have iommu.

Also, could we have more generic iommu-map description like the one for
sdm845 at [1] ?

-- 
regards,
Stan