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Mon, 29 Sep 2025 16:13:04 +0000 Message-ID: <59375a10-2a5b-45ed-9a4c-76884c0fe3c6@intel.com> Date: Mon, 29 Sep 2025 19:12:54 +0300 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/4] mmc: sdhci-msm: Add Device tree parsing logic for DLL settings To: Ram Prakash Gupta , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: , , , , , , , , , , Sachin Gupta References: <20250929113515.26752-1-quic_rampraka@quicinc.com> <20250929113515.26752-4-quic_rampraka@quicinc.com> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <20250929113515.26752-4-quic_rampraka@quicinc.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: DB8PR06CA0050.eurprd06.prod.outlook.com (2603:10a6:10:120::24) To IA1PR11MB7198.namprd11.prod.outlook.com (2603:10b6:208:419::15) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR11MB7198:EE_|DS0PR11MB7829:EE_ X-MS-Office365-Filtering-Correlation-Id: e36cb773-0fad-4afb-194b-08ddff730fd7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014|7053199007; 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> }; > > +/* > + * DLL registers which needs be programmed with HSR settings. > + * Add any new register only at the end and don't change the > + * sequence. > + */ > +struct sdhci_msm_dll { > + u32 dll_config[2]; > + u32 dll_config_2[2]; > + u32 dll_config_3[2]; > + u32 dll_usr_ctl[2]; > + u32 ddr_config[2]; > +}; > + > struct sdhci_msm_host { > struct platform_device *pdev; > void __iomem *core_mem; /* MSM SDCC mapped address */ > @@ -273,6 +286,7 @@ struct sdhci_msm_host { > struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ > /* core, iface, cal and sleep clocks */ > struct clk_bulk_data bulk_clks[4]; > + struct sdhci_msm_dll dll; > #ifdef CONFIG_MMC_CRYPTO > struct qcom_ice *ice; > #endif > @@ -301,6 +315,7 @@ struct sdhci_msm_host { > u32 dll_config; > u32 ddr_config; > bool vqmmc_enabled; > + bool artanis_dll; > }; > > static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host) > @@ -2516,6 +2531,73 @@ static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host) > return ret; > } > > +static int sdhci_msm_dt_get_array(struct device *dev, const char *prop_name, > + u32 **dll_table, int *len) > +{ > + struct device_node *np = dev->of_node; > + u32 *arr = NULL; > + int ret = 0, sz = 0; > + > + if (!np) > + return -ENODEV; > + if (!of_get_property(np, prop_name, &sz)) > + return -EINVAL; > + > + sz = sz / sizeof(*arr); > + if (sz <= 0) > + return -EINVAL; > + > + arr = kcalloc(sz, sizeof(*arr), GFP_KERNEL); > + if (!arr) > + return -ENOMEM; > + > + ret = of_property_read_u32_array(np, prop_name, arr, sz); > + if (ret) { > + dev_err(dev, "%s failed reading array %d\n", prop_name, ret); > + *len = 0; > + return ret; > + } > + > + *dll_table = arr; > + *len = sz; > + > + return ret; > +} > + > +static int sdhci_msm_dt_parse_dll_info(struct device *dev, struct sdhci_msm_host *msm_host) > +{ > + int dll_table_len, dll_reg_count; > + u32 *dll_table = NULL; > + int i, j; > + > + msm_host->artanis_dll = false; > + > + if (sdhci_msm_dt_get_array(dev, "qcom,dll-hsr-list", > + &dll_table, &dll_table_len)) > + return -EINVAL; > + > + dll_reg_count = sizeof(struct sdhci_msm_dll) / sizeof(u32); > + > + if (dll_table_len != dll_reg_count) { > + dev_err(dev, "Number of HSR entries are not matching\n"); > + return -EINVAL; > + } > + > + for (i = 0, j = 0; j < 2; i = i + 5, j++) { > + msm_host->dll.dll_config[j] = dll_table[i]; > + msm_host->dll.dll_config_2[j] = dll_table[i + 1]; > + msm_host->dll.dll_config_3[j] = dll_table[i + 2]; > + msm_host->dll.dll_usr_ctl[j] = dll_table[i + 3]; > + msm_host->dll.ddr_config[j] = dll_table[i + 4]; > + } Kind of begs the question, why the driver and the DT have to be in a different order. It might be simpler to have: struct sdhci_msm_dll { u32 dll_config; u32 dll_config_2; u32 dll_config_3; u32 dll_usr_ctl; u32 ddr_config; }; And: struct sdhci_msm_dll dll[2]; And then dereference like: msm_host->dll[index].dll_config_3 Also then you could perhaps use something like: of_property_read_variable_u32_array(np, "qcom,dll-hsr-list", msm_host->dll, 10, 10) instead of most of sdhci_msm_dt_get_array() > + > + msm_host->artanis_dll = true; > + > + kfree(dll_table); > + > + return 0; > +} > + > static int sdhci_msm_probe(struct platform_device *pdev) > { > struct sdhci_host *host; > @@ -2562,6 +2644,15 @@ static int sdhci_msm_probe(struct platform_device *pdev) > > msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; > > + /* > + * Parse HSR dll only when property is present in DT. > + */ > + if (of_find_property(node, "qcom,dll-hsr-list", NULL)) { > + ret = sdhci_msm_dt_parse_dll_info(&pdev->dev, msm_host); > + if (ret) > + return ret; > + } > + > ret = sdhci_msm_gcc_reset(&pdev->dev, host); > if (ret) > return ret;