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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6ecf8ca6sm881270266b.118.2025.04.30.00.46.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Apr 2025 00:46:27 -0700 (PDT) Message-ID: <59e3e34d-83b6-4f83-be4c-eeaaba9a353e@oss.qualcomm.com> Date: Wed, 30 Apr 2025 09:46:24 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC/WIP 1/4] arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC To: Abhinav Kumar , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jessica Zhang , Abhinav Kumar , Abel Vesa , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250424-sm8750-display-dts-v1-0-6fb22ca95f38@linaro.org> <20250424-sm8750-display-dts-v1-1-6fb22ca95f38@linaro.org> <81205948-ae43-44ee-aa07-e490ea3bba23@oss.qualcomm.com> <97ae84c6-0807-4b19-a474-ba76cc049da9@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <97ae84c6-0807-4b19-a474-ba76cc049da9@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: jygZqeLcpIeqre68VKjMPYAR_uYusf7n X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDMwMDA1MyBTYWx0ZWRfXy2cyxuVgAyxK /7R6V12uKsGb7xqUzDQQTlZo8vzs9ck2wNjF7B+Rzbmj8Dx5Rsr/EZmGnZnEK0QzofcGVx3k3vh eaEKkhhcVdQMbGQgZaRNtZmQE/02r21OWoi5ECsvypFO1pi47QKqzpW/eIu8VR3xEqjMrD2kwyz p4lJnFaX3GYiNw0YGr+xMHha5dcwzgbt0GSkZxi3JIabPjARegMnzJ8mXtlYnjx4P4zYl3q9v3Q meU/plxXvKXO3xh/BR+oG4qP6ryYn9aFZmCl7lGg9YZr6kvXSIhHCALTFRje+MceTacru9op4du Cjd/pPjCzfDpvp84ADGeAyc+7M5giuvfu0m2D57lygtNxBTfjpfhdQtOrg6emnenMKz8kVK31EV wqoaglGRCJU1aR518U5sZT/Jptb3HronLVPhPjCTDBFguCJIT07SXfmvuqgtopCFGlqymyhb X-Authority-Analysis: v=2.4 cv=b5qy4sGx c=1 sm=1 tr=0 ts=6811d554 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=bmsyZSe9DYnGDotP4YEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: jygZqeLcpIeqre68VKjMPYAR_uYusf7n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-30_02,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 mlxscore=0 impostorscore=0 malwarescore=0 spamscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504300053 On 4/30/25 1:07 AM, Abhinav Kumar wrote: > > > On 4/28/2025 2:31 PM, Konrad Dybcio wrote: >> On 4/24/25 3:04 PM, Krzysztof Kozlowski wrote: >>> Add device nodes for entire display: MDSS, DPU, DSI, DSI PHYs, >>> DisplayPort and Display Clock Controller. >>> >>> Signed-off-by: Krzysztof Kozlowski >>> >>> --- >> >> [...] >> >>> +                mdp_opp_table: opp-table { >>> +                    compatible = "operating-points-v2"; >>> + >> >> The computer tells me there's also a 156 MHz rate @ SVS_D1 >> >> Maybe Abhinav could chime in whether we should add it or not >> > > Yes I also see a 156Mhz for LOW_SVS_D1 but we had a similar entry even for sm8650 and did not publish it in the dt. > > It was present till sm8450.dtsi but dropped in sm8550/sm8650 even though LOW_SVS_D1 is present even on those. > > I think the reason could be that the displays being used on the reference boards will need a pixel clock of atleast >= low_svs and the MDP clock usually depends on the value of the DSI pixel clock (which has a fixed relationship to the byte clock) to maintain the data rate. So as a result perhaps even if we add it, for most displays this level will be unused. > > If we end up using displays which are so small that the pixel clock requirement will be even lower than low_svs, we can add those. > > OR as an alternative, we can leave this patch as it is and add the low_svs_d1 for all chipsets which support it together in another series that way it will have the full context of why we are adding it otherwise it will look odd again of why sm8550/sm8650 was left out but added in sm8750. I would assume that with VRR even fancy panels at low refresh rate (in the 1-5 Hz range) may make use of this, so I would be happy to go with option 2 > >> [...] >> >>> +                mdss_dsi_opp_table: opp-table { >>> +                    compatible = "operating-points-v2"; >>> + >> >> Similarly there's a 140.63 MHz rate at SVS_D1, but it seems odd >> with the decimals > > For this one, yes its true that LOW_SVS_D1 is 140.63Mhz for sm8750 but this voltage corner was somehow never used for DSI byte clock again I am thinking this is because for the display resolutions we use, we will always be >= low_svs so the low_svs_d1 will never hit even if we add it. Alright Konrad