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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a83dsm284849766b.156.2024.11.30.06.32.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 30 Nov 2024 06:32:54 -0800 (PST) Message-ID: <5c3d91e3-e9d3-4e8d-bd4f-f7cbe765dddc@oss.qualcomm.com> Date: Sat, 30 Nov 2024 15:32:51 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 To: Dmitry Baryshkov , Jagadeesh Kona Cc: Brian Masney , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ajit Pandey , Imran Shaik , Taniya Das , Satya Priya Kakitapalli , Shivnandan Kumar References: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com> <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-2-074e0fb80b33@quicinc.com> <9179759d-7af1-409f-8130-1136c9ae4ecd@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: YNznuNufs5rA5LQIdlzMOsntBAh2P5VJ X-Proofpoint-GUID: YNznuNufs5rA5LQIdlzMOsntBAh2P5VJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 impostorscore=0 malwarescore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2411300120 On 14.11.2024 11:48 PM, Dmitry Baryshkov wrote: > On Mon, Nov 11, 2024 at 06:39:48PM +0530, Jagadeesh Kona wrote: >> >> >> On 10/17/2024 9:12 PM, Brian Masney wrote: >>> On Thu, Oct 17, 2024 at 02:58:31PM +0530, Jagadeesh Kona wrote: >>>> + cpu0_opp_table: opp-table-cpu0 { >>>> + compatible = "operating-points-v2"; >>>> + opp-shared; >>>> + >>>> + cpu0_opp_1267mhz: opp-1267200000 { >>>> + opp-hz = /bits/ 64 <1267200000>; >>>> + opp-peak-kBps = <6220800 29491200>; >>>> + }; >>>> + >>>> + cpu0_opp_1363mhz: opp-1363200000 { >>>> + opp-hz = /bits/ 64 <1363200000>; >>>> + opp-peak-kBps = <6220800 29491200>; >>>> + }; >>> >>> [snip] >>> >>>> + cpu4_opp_table: opp-table-cpu4 { >>>> + compatible = "operating-points-v2"; >>>> + opp-shared; >>>> + >>>> + cpu4_opp_1267mhz: opp-1267200000 { >>>> + opp-hz = /bits/ 64 <1267200000>; >>>> + opp-peak-kBps = <6220800 29491200>; >>>> + }; >>>> + >>>> + cpu4_opp_1363mhz: opp-1363200000 { >>>> + opp-hz = /bits/ 64 <1363200000>; >>>> + opp-peak-kBps = <6220800 29491200>; >>>> + }; >>> >>> There's no functional differences in the cpu0 and cpu4 opp tables. Can >>> a single table be used? >>> >>> This aligns with my recollection that this particular SoC only has the >>> gold cores. >>> >>> Brian >>> >> >> Thanks Brian for your review. Sorry for the delayed response. >> >> We require separate OPP tables for CPU0 and CPU4 to allow independent >> scaling of DDR and L3 frequencies for each CPU domain, with the final >> DDR and L3 frequencies being an aggregate of both. >> >> If we use a single OPP table for both CPU domains, then _allocate_opp_table() [1] >> won't be invoked for CPU4. As a result both CPU devices will end up in sharing >> the same ICC path handle, which could lead to one CPU device overwriting the bandwidth >> votes of other. Oh that's a fun find.. clocks get the same treatment.. very bad, but may explain some schroedingerbugs. Taking a peek at some code paths, wouldn't dropping opp-shared solve our issues? dev_pm_opp_set_sharing_cpus() overrides it Konrad