From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Pankaj Patil <pankaj.patil@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>
Cc: Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>,
Maulik Shah <maulik.shah@oss.qualcomm.com>,
Sibi Sankar <sibi.sankar@oss.qualcomm.com>,
Taniya Das <taniya.das@oss.qualcomm.com>,
Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>,
Qiang Yu <qiang.yu@oss.qualcomm.com>,
Manaf Meethalavalappu Pallikunhi
<manaf.pallikunhi@oss.qualcomm.com>,
Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>,
Abel Vesa <abelvesa@kernel.org>
Subject: Re: [PATCH v4 3/4] arm64: dts: qcom: Introduce Glymur base dtsi
Date: Wed, 14 Jan 2026 14:47:57 +0100 [thread overview]
Message-ID: <5cd1f4f5-808d-46cf-a44a-ee5428987727@oss.qualcomm.com> (raw)
In-Reply-To: <ad105956-3192-4559-9d53-3b526f2fa361@oss.qualcomm.com>
On 1/14/26 11:29 AM, Pankaj Patil wrote:
> On 1/14/2026 9:47 AM, Bjorn Andersson wrote:
>> On Mon, Jan 12, 2026 at 05:52:36PM +0530, Pankaj Patil wrote:
>>> Introduce the base device tree support for Glymur – Qualcomm's
>>> next-generation compute SoC. The new glymur.dtsi describes the core SoC
>>> components, including:
>>>
>>> - CPUs and CPU topology
>>> - Interrupt controller and TLMM
>>> - GCC,DISPCC and RPMHCC clock controllers
>>> - Reserved memory and interconnects
>>> - APPS and PCIe SMMU and firmware SCM
>>> - Watchdog, RPMHPD, APPS RSC and SRAM
>>> - PSCI and PMU nodes
>>> - QUPv3 serial engines
>>> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS
>>> - PDP0 mailbox, IPCC and AOSS
>>> - Display clock controller
>>> - SPMI PMIC arbiter with SPMI0/1/2 buses
>>> - SMP2P nodes
>>> - TSENS and thermal zones (8 instances, 92 sensors)
>>>
>>> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104,
>>> PMH0110 along with temp-alarm and GPIO nodes needed on Glymur
>>>
>>> Enabled PCIe controllers and associated PHY to support boot to
>>> shell with nvme storage,
>>> List of PCIe instances enabled:
>>>
>>> - PCIe3b
>>> - PCIe4
>>> - PCIe5
>>> - PCIe6
>>>
>>
>> Why didn't you run "make qcom/glymur-crd.dtb CHECK_DTBS=1" before
>> sending patches to the mailing list?!
>>
>> It would taken you 30 seconds to conclude that I can't do anything with
>> these patches.
>>
>> Regards,
>> Bjorn
>
> I've ran the bindings check, dt-bindings specified as dependencies will fix the errors
> Additionally, I'll drop qup-memory from interconnects for serial and spi in next rev,
> which cause the bindings errors, this was missed
The SPI flavor of QUPs is definitely DMA-capable and I don't see how it
could error out with the current bindings definition
Konrad
next prev parent reply other threads:[~2026-01-14 13:48 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-12 12:22 [PATCH v4 0/4] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
2026-01-12 12:22 ` [PATCH v4 1/4] dt-bindings: arm: qcom: Document Glymur SoC and board Pankaj Patil
2026-01-12 12:32 ` Krzysztof Kozlowski
2026-01-12 12:22 ` [PATCH v4 2/4] arm64: defconfig: Enable Glymur configs for boot to shell Pankaj Patil
2026-01-12 12:34 ` Krzysztof Kozlowski
2026-01-12 12:22 ` [PATCH v4 3/4] arm64: dts: qcom: Introduce Glymur base dtsi Pankaj Patil
2026-01-14 4:17 ` Bjorn Andersson
2026-01-14 10:29 ` Pankaj Patil
2026-01-14 13:47 ` Konrad Dybcio [this message]
2026-01-16 6:40 ` Pankaj Patil
2026-01-14 13:45 ` Konrad Dybcio
2026-01-19 6:21 ` Qiang Yu
2026-01-15 7:51 ` Krzysztof Kozlowski
2026-01-12 12:22 ` [PATCH v4 4/4] arm64: dts: qcom: glymur: Enable Glymur CRD board support Pankaj Patil
2026-01-14 13:50 ` Konrad Dybcio
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