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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6629f7cbc78sm1453211a12.17.2026.03.10.06.22.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Mar 2026 06:22:33 -0700 (PDT) Message-ID: <5ce56237-1a57-4dc0-99f5-c6c813875e08@oss.qualcomm.com> Date: Tue, 10 Mar 2026 14:22:31 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] dt-bindings: clock: qcom: document the Fillmore Global Clock Controller To: Aelin Reidel , Krzysztof Kozlowski Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@mainlining.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht References: <20260308-fillmore-clks-v1-0-976d9a6bebe7@mainlining.org> <20260308-fillmore-clks-v1-1-976d9a6bebe7@mainlining.org> <20260309-quirky-heavy-armadillo-9f92bc@quoll> <386d5f66-1f22-42dc-9696-05b1e54d7577@mainlining.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <386d5f66-1f22-42dc-9696-05b1e54d7577@mainlining.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDExNyBTYWx0ZWRfXyJjjf7Xogs+w JRoz8RInfK3ni0ZrmY6OFrAMKTzfJs1lQCg/4XLYSgPVzMV1jMta9d+VWQBD4mEKLcQiLN//0Vn oe4i5WQ4vg25mWfriHL6cUpbTwS+qi4KFhItT9e075Hdr5nJkke4KFHhIRYNwm4tpjyF5kNQLKh yST9yTtb0sTmM5cdh0MsfF1QYkcSvcinteUrnzk/xg6YK+InwsS4N2iciILOKX8/9I3jCXMSSHr xB1uxFryX6z5mDST2EmCPMZPLBMDPKxIJTkRrdQw2h7hpsLr8jYe0+pWXs3wdFR3S6nqUS7mVQ9 M2ttl9NNRspfzLcL9CJlAjMwrfQjd3RaXAVeMDj6tM0wJ4z1aYVtfX1pUGKHc+Ymr+2Yc2V/AtV AGygmUfF9c9LTLTDW6YT6Ypivjcvsu69rYgimKGQ0c4V+4nxKhlRFi5bRpSzsh6MVkG4XG+Sz5D /JoVR3vhboWCpsNPXsQ== X-Proofpoint-GUID: BhOV0ciKQmzkO1IABAsJlaLYTI903B3P X-Authority-Analysis: v=2.4 cv=KLxXzVFo c=1 sm=1 tr=0 ts=69b01b1c cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=gEfo2CItAAAA:8 a=OuZLqq7tAAAA:8 a=kGAoTktFa5V21D_EptYA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=sptkURWiP4Gy88Gu7hUp:22 a=AKGiAy9iJ-JzxKVHQNES:22 X-Proofpoint-ORIG-GUID: BhOV0ciKQmzkO1IABAsJlaLYTI903B3P X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_02,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 bulkscore=0 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603100117 On 3/9/26 3:56 PM, Aelin Reidel wrote: > On 3/9/26 8:38 AM, Krzysztof Kozlowski wrote: >> On Sun, Mar 08, 2026 at 01:39:27AM +0100, Aelin Reidel wrote: >>> Add bindings documentation for the Fillmore (e.g. SM7450) Global Clock >>> Controller. >>> >>> Signed-off-by: Aelin Reidel >>> --- >>> .../bindings/clock/qcom,fillmore-gcc.yaml | 60 +++++++ >>> include/dt-bindings/clock/qcom,fillmore-gcc.h | 195 +++++++++++++++++++++ >>> 2 files changed, 255 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/clock/qcom,fillmore-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,fillmore-gcc.yaml >>> new file mode 100644 >>> index 0000000000000000000000000000000000000000..0eb12a52968edc7961681f0e965b4d6da0858b9c >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/qcom,fillmore-gcc.yaml >>> @@ -0,0 +1,60 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/clock/qcom,fillmore-gcc.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm Global Clock & Reset Controller on Fillmore >>> + >>> +maintainers: >>> + - Aelin Reidel >>> + >>> +description: | >>> + Qualcomm global clock control module provides the clocks, resets and power >>> + domains on Fillmore. >>> + >>> + See also: include/dt-bindings/clock/qcom,fillmore-gcc.h >>> + >>> +properties: >>> + compatible: >>> + const: qcom,fillmore-gcc >>> + >>> + clocks: >>> + items: >>> + - description: Board XO source >>> + - description: Sleep clock source >>> + - description: PCIE 0 Pipe clock source >> >> Aer you sure there is no PCIE 1? Because I would be dissapointed if it >> is being added later. With PCIE 1 clock this would be basically Milos >> GCC. >> >> Best regards, >> Krzysztof > > Yes, there is no PCIE 1. Fillmore has only PCIE 0, which is used for WiFi/BT > and is Gen 3 1-lane. I concur Konrad