From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org,
lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com,
konradybcio@kernel.org, daniel.lezcano@linaro.org,
sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com,
lee@kernel.org, rafael@kernel.org,
subbaraman.narayanamurthy@oss.qualcomm.com,
david.collins@oss.qualcomm.com,
anjelique.melendez@oss.qualcomm.com,
kamal.wadhwa@oss.qualcomm.com, rui.zhang@intel.com,
lukasz.luba@arm.com, devicetree@vger.kernel.org,
linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
cros-qcom-dts-watchers@chromium.org, quic_kotarake@quicinc.com,
neil.armstrong@linaro.org, stephan.gerhold@linaro.org,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH V7 3/5] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
Date: Tue, 16 Sep 2025 19:58:18 +0530 [thread overview]
Message-ID: <5d662148-408f-49e1-a769-2a5d61371cae@oss.qualcomm.com> (raw)
In-Reply-To: <20250829-classic-dynamic-clam-addbd8@kuoka>
Hi Krzysztof,
On 8/29/2025 12:49 PM, Krzysztof Kozlowski wrote:
> On Tue, Aug 26, 2025 at 02:06:55PM +0530, Jishnu Prakash wrote:
>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>>
>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>> going through PBS(Programmable Boot Sequence) firmware through a single
>> register interface. This interface is implemented on SDAM (Shared
>> Direct Access Memory) peripherals on the master PMIC PMK8550 rather
>> than a dedicated ADC peripheral.
>>
>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
>> channels and virtual channels (combination of ADC channel number and
>> PMIC SID number) per PMIC, to be used by clients of this device. Also
>> update SPMI PMIC bindings to allow ADC5 Gen3 as adc@ subnode.
>>
>> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>> ---
>> Changes since v6:
>> - Updated SPMI PMIC bindings to allow ADC5 Gen3 as adc@ subnode and
>> copyright license in newly added files.
>
> So you did not implement my requests/comments from v5? I did not request
> above, I had many, many other comments.
>
>
In my v6 patch, I had implemented all the changes you requested in
my v5 patch, that is what I had meant by the last part ('addressed other reviewer comments').
I will update the below section when pushing my next patch series
to list out all the changes explicitly.
>
>>
>> Changes since v5:
>> - Added more details in binding description explaining how number
>> of SDAM peripherals used for ADC is allocated per SoC.
>> - Renamed per-PMIC binding files listing ADC channel macro names
>> and addressed other reviewer comments.
>>
>> Changes since v4:
>> - Added ADC5 Gen3 documentation in a separate new file to avoid complicating
>> existing VADC documentation file further to accomodate this device, as
>> suggested by reviewer.
>>
>> Changes since v3:
>> - Added ADC5 Gen3 documentation changes in existing qcom,spmi-vadc.yaml file
>> instead of adding separate file and updated top-level constraints in documentation
>> file based on discussion with reviewers.
>> - Dropped default SID definitions.
>> - Addressed other reviewer comments.
>>
>> Changes since v2:
>> - Moved ADC5 Gen3 documentation into a separate new file.
>>
...
>> +
>> + The interface is implemented on SDAM (Shared Direct Access Memory) peripherals
>> + on the master PMIC rather than a dedicated ADC peripheral. The number of PMIC
>> + SDAM peripherals allocated for ADC is not correlated with the PMIC used, it is
>> + programmed in FW (PBS) and is fixed per SOC, based on the SOC requirements.
>> + All boards using a particular (SOC + master PMIC) combination will have the
>> + same number of ADC SDAMs supported on that PMIC.
>> +
>> +properties:
>> + compatible:
>> + const: qcom,spmi-adc5-gen3
>> +
>> + reg:
>> + items:
>> + - description: SDAM0 base address in the SPMI PMIC register map
>> + - description: SDAM1 base address
>> + minItems: 1
>> +
>> + '#address-cells':
>> + const: 1
>> +
>> + '#size-cells':
>> + const: 0
>> +
>> + '#io-channel-cells':
>> + const: 1
>> +
>> + "#thermal-sensor-cells":
>
> Nothing improved here, still mess with quotes.
I will fix this and check for any other things to fix
before pushing the next patch.
>
> I am not going to check the rest of comments, because:
> 1. Your changelog is vague and claims you did not implement them,
> 2. b4 diff does not work, base-commit is unknown.
> 3. Main changelog is even more vague.
>
> You make it difficult for us to review your patches, fine. You will get:
>
> NAK (plus one more comment below)
>
>> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
>> index ef07ecd4d585..b1b89e874316 100644
>> --- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
>> +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
>> @@ -300,4 +300,83 @@
>> #define ADC7_SBUx 0x94
>> #define ADC7_VBAT_2S_MID 0x96
>>
>> +/* ADC channels for PMIC5 Gen3 */
>> +
>> +#define ADC5_GEN3_REF_GND 0x00
>> +#define ADC5_GEN3_1P25VREF 0x01
>> +#define ADC5_GEN3_VREF_VADC 0x02
>> +#define ADC5_GEN3_DIE_TEMP 0x03
>> +
>> +#define ADC5_GEN3_AMUX1_THM 0x04
>> +#define ADC5_GEN3_AMUX2_THM 0x05
>> +#define ADC5_GEN3_AMUX3_THM 0x06
>> +#define ADC5_GEN3_AMUX4_THM 0x07
>> +#define ADC5_GEN3_AMUX5_THM 0x08
>> +#define ADC5_GEN3_AMUX6_THM 0x09
>> +#define ADC5_GEN3_AMUX1_GPIO 0x0a
>> +#define ADC5_GEN3_AMUX2_GPIO 0x0b
>> +#define ADC5_GEN3_AMUX3_GPIO 0x0c
>> +#define ADC5_GEN3_AMUX4_GPIO 0x0d
>> +
>> +#define ADC5_GEN3_CHG_TEMP 0x10
>> +#define ADC5_GEN3_USB_SNS_V_16 0x11
>> +#define ADC5_GEN3_VIN_DIV16_MUX 0x12
>> +#define ADC5_GEN3_VREF_BAT_THERM 0x15
>
> You cannot have empty spaces in ID constants. These are abstract
> numbers.
>
> Otherwise please point me to driver using this constant.
These constants are for ADC channel numbers, which are fixed in HW.
They are used in this driver: drivers/iio/adc/qcom-spmi-adc5-gen3.c,
which is added in patch 4 of this series.
They can be found in the array named adc5_gen3_chans_pmic[].
Thanks,
Jishnu
>
> Best regards,
> Krzysztof
>
next prev parent reply other threads:[~2025-09-16 14:28 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-26 8:36 [PATCH V7 0/5] Add support for QCOM SPMI PMIC5 Gen3 ADC Jishnu Prakash
2025-08-26 8:36 ` [PATCH V7 1/5] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder Jishnu Prakash
2025-08-26 8:36 ` [PATCH V7 2/5] dt-bindings: iio: adc: Split out QCOM VADC channel properties Jishnu Prakash
2025-08-26 8:36 ` [PATCH V7 3/5] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC Jishnu Prakash
2025-08-29 7:19 ` Krzysztof Kozlowski
2025-09-16 14:28 ` Jishnu Prakash [this message]
2025-09-17 0:29 ` Krzysztof Kozlowski
2025-09-17 19:47 ` Jishnu Prakash
2025-09-18 0:15 ` Krzysztof Kozlowski
2025-09-19 14:47 ` Jishnu Prakash
2025-09-27 13:47 ` Jonathan Cameron
2025-10-04 2:41 ` Jishnu Prakash
2025-10-04 6:52 ` Krzysztof Kozlowski
2025-10-08 14:20 ` Jishnu Prakash
2025-10-08 23:52 ` Krzysztof Kozlowski
2025-10-17 11:18 ` Jishnu Prakash
2025-10-17 13:40 ` Krzysztof Kozlowski
2025-10-20 12:51 ` Konrad Dybcio
2025-10-20 15:55 ` Krzysztof Kozlowski
2025-10-22 11:02 ` Konrad Dybcio
2025-10-27 16:30 ` Krzysztof Kozlowski
2025-11-01 2:20 ` Jishnu Prakash
2025-08-26 8:36 ` [PATCH V7 4/5] " Jishnu Prakash
2025-08-30 17:42 ` Jonathan Cameron
2025-09-17 19:47 ` Jishnu Prakash
2025-08-26 8:36 ` [PATCH V7 5/5] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring Jishnu Prakash
2025-08-27 1:44 ` Dmitry Baryshkov
2025-08-29 7:14 ` Krzysztof Kozlowski
2025-08-30 17:58 ` Jonathan Cameron
2025-09-17 19:47 ` Jishnu Prakash
2025-08-29 7:11 ` [PATCH V7 0/5] Add support for QCOM SPMI PMIC5 Gen3 ADC Krzysztof Kozlowski
2025-09-16 14:27 ` Jishnu Prakash
2025-08-29 7:12 ` Krzysztof Kozlowski
2025-08-29 8:09 ` Dmitry Baryshkov
2025-08-29 9:11 ` Krzysztof Kozlowski
2025-08-29 9:20 ` Dmitry Baryshkov
2025-08-29 16:31 ` Jonathan Cameron
2025-09-17 19:43 ` Bjorn Andersson
2025-09-19 14:47 ` Jishnu Prakash
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5d662148-408f-49e1-a769-2a5d61371cae@oss.qualcomm.com \
--to=jishnu.prakash@oss.qualcomm.com \
--cc=Jonathan.Cameron@huawei.com \
--cc=agross@kernel.org \
--cc=amitk@kernel.org \
--cc=andersson@kernel.org \
--cc=anjelique.melendez@oss.qualcomm.com \
--cc=conor+dt@kernel.org \
--cc=cros-qcom-dts-watchers@chromium.org \
--cc=daniel.lezcano@linaro.org \
--cc=david.collins@oss.qualcomm.com \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@oss.qualcomm.com \
--cc=jic23@kernel.org \
--cc=kamal.wadhwa@oss.qualcomm.com \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=krzysztof.kozlowski@linaro.org \
--cc=lee@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-iio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=lukasz.luba@arm.com \
--cc=lumag@kernel.org \
--cc=neil.armstrong@linaro.org \
--cc=quic_kotarake@quicinc.com \
--cc=rafael@kernel.org \
--cc=robh@kernel.org \
--cc=rui.zhang@intel.com \
--cc=sboyd@kernel.org \
--cc=stephan.gerhold@linaro.org \
--cc=subbaraman.narayanamurthy@oss.qualcomm.com \
--cc=thara.gopinath@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox