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Mon, 28 Apr 2025 22:48:54 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53SMmsNg002588 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Apr 2025 22:48:54 GMT Received: from [10.134.71.99] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Apr 2025 15:48:53 -0700 Message-ID: <61310672-171e-4496-ae6a-ad31fbdb2b83@quicinc.com> Date: Mon, 28 Apr 2025 15:48:52 -0700 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/8] drm/msm/dpu: program master INTF value To: Dmitry Baryshkov , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter CC: , , , , "Neil Armstrong" References: <20250307-dpu-active-ctl-v3-0-5d20655f10ca@linaro.org> <20250307-dpu-active-ctl-v3-2-5d20655f10ca@linaro.org> Content-Language: en-US From: Jessica Zhang In-Reply-To: <20250307-dpu-active-ctl-v3-2-5d20655f10ca@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI4MDE4MiBTYWx0ZWRfX4upFlcHnLI08 cD5weaYf/VbcAcsWqp8kiHNbg85HhbiDedc6i6l6R5oZNv6zkWvcXQEolODnFwpym224XGl/dLX H2cgMX/NcGtO3ZTOWgCzKTTBh+Yl0nzj6xBz3CooEu9nMMz1i5eeWTYaYcjxDb9NVOqMsyFbCys rmTPpX/1r/GIkEq9cpOgFDpN8RW1TjzoznUu9JFVkFWgPpQ5HzuTjabZl/1+mxbuVZFyB1okRr8 MhbpdTz6xJ2n1MRJnfIMX9AyOnI4Xq8PafwledbOzB78iTFOleaRuaTMpqu8fpcl58Ckazt67kF 7/Ex0aDWz67pVQO7sx+UTFNyHVoDxFmfnKt1ZvX5RnsFuTQ5VfVO8wpvKnYAxDSizqCytbJLeYK 2BJ781zkP3RQEDbcGh9Oqb4xa1VmBF9eyZcxM0e7q674h/JKzS6lLVyShJ/XDccETovNsdPJ X-Proofpoint-GUID: jZ6lApvq3ZJIw4APME12GlatR0Jf897T X-Proofpoint-ORIG-GUID: jZ6lApvq3ZJIw4APME12GlatR0Jf897T X-Authority-Analysis: v=2.4 cv=C8fpyRP+ c=1 sm=1 tr=0 ts=681005d6 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=tVI0ZWmoAAAA:8 a=COk6AnOGAAAA:8 a=rxETW27_YrsaSjKoF0MA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=-BPWgnxRz2uhmvdm1NTO:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-28_09,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504280182 On 3/6/2025 10:24 PM, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov > > If several interfaces are being handled through a single CTL, a main > ('master') INTF needs to be programmed into a separate register. Write > corresponding value into that register. > > Co-developed-by: Marijn Suijten > Signed-off-by: Marijn Suijten > Reviewed-by: Marijn Suijten > Tested-by: Neil Armstrong # on SM8550-QRD > Signed-off-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 12 ++++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ > 2 files changed, 14 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index cef3bfaa4af82ebc55fb8cf76adef3075c7d73e3..21f4d403e3c278d83d7eaa6a7dd53f471d9e296d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -603,6 +603,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, > DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active); > DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active); > > + if (cfg->intf_master) > + DPU_REG_WRITE(c, CTL_INTF_MASTER, BIT(cfg->intf_master - INTF_0)); > + > if (cfg->cdm) > DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm); > } > @@ -645,6 +648,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, > { > struct dpu_hw_blk_reg_map *c = &ctx->hw; > u32 intf_active = 0; > + u32 intf_master = 0; > u32 wb_active = 0; > u32 cwb_active = 0; > u32 merge3d_active = 0; > @@ -672,6 +676,14 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, > intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); > intf_active &= ~BIT(cfg->intf - INTF_0); > DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); > + > + intf_master = DPU_REG_READ(c, CTL_INTF_MASTER); > + > + /* Unset this intf as master, if it is the current master */ > + if (intf_master == BIT(cfg->intf - INTF_0)) { > + DPU_DEBUG_DRIVER("Unsetting INTF_%d master\n", cfg->intf - INTF_0); > + DPU_REG_WRITE(c, CTL_INTF_MASTER, 0); > + } > } > > if (cfg->cwb) { > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > index 080a9550a0cc6530b4115165dd737857b6213d15..cea23436fc80a17a679363a47f9f287b72623a1c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > @@ -36,6 +36,7 @@ struct dpu_hw_stage_cfg { > /** > * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface > * @intf : Interface id > + * @intf_master: Master interface id in the dual pipe topology > * @mode_3d: 3d mux configuration > * @merge_3d: 3d merge block used > * @intf_mode_sel: Interface mode, cmd / vid > @@ -46,6 +47,7 @@ struct dpu_hw_stage_cfg { > */ > struct dpu_hw_intf_cfg { > enum dpu_intf intf; > + enum dpu_intf intf_master; > enum dpu_wb wb; > enum dpu_3d_blend_mode mode_3d; > enum dpu_merge_3d merge_3d; >