From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kumar Gala Subject: Re: [PATCH v2 03/10] qcom: spm: Add Subsystem Power Manager (SPM) driver for QCOM chipsets Date: Thu, 14 Aug 2014 11:09:48 -0500 Message-ID: <61C7FA07-985E-41DC-AD3F-BCFA0920ED0E@codeaurora.org> References: <1407872640-6732-1-git-send-email-lina.iyer@linaro.org> <1407872640-6732-4-git-send-email-lina.iyer@linaro.org> Mime-Version: 1.0 (Mac OS X Mail 7.3 \(1878.6\)) Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Received: from smtp.codeaurora.org ([198.145.11.231]:43663 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753059AbaHNQJx convert rfc822-to-8bit (ORCPT ); Thu, 14 Aug 2014 12:09:53 -0400 In-Reply-To: <1407872640-6732-4-git-send-email-lina.iyer@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Lina Iyer Cc: Daniel Lezcano , Kevin Hilman , Amit Kucheria , Stephen Boyd , David Brown , linux-arm-msm@vger.kernel.org, msivasub@codeaurora.org, Praveen Chidamabram , Murali Nalajala On Aug 12, 2014, at 2:43 PM, Lina Iyer wrote: >=20 > diff --git a/Documentation/devicetree/bindings/arm/msm/spm-v2.txt b/D= ocumentation/devicetree/bindings/arm/msm/spm-v2.txt > new file mode 100644 > index 0000000..3130f4b > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/msm/spm-v2.txt > @@ -0,0 +1,62 @@ > +* MSM Subsystem Power Manager (spm-v2) > + > +S4 generation of MSMs have SPM hardware blocks to control the Applic= ation > +Processor Sub-System power. These SPM blocks run individual state ma= chine > +to determine what the core (L2 or Krait/Scorpion) would do when the = WFI > +instruction is executed by the core. > + > +The devicetree representation of the SPM block should be: > + > +Required properties > + > +- compatible: Could be one of - > + "qcom,spm-v2.1" > + "qcom,spm-v3.0" > +- reg: The physical address and the size of the SPM's memory mapped = registers > +- qcom,cpu: phandle for the CPU that the SPM block is attached to. O= n targets > + that dont support CPU phandles the driver would support qcom,core-i= d. > + This field is required on only for SPMs that control the CPU. > +- qcom,saw2-cfg: SAW2 configuration register Can we change this to qcom,saw2-clk-div as that is what is really getti= ng set, I know there are a few other fields in the saw2-cfg register, b= ut I=92m pretty sure we arent ever really setting those from DT.=20 > +- qcom,saw2-spm-dly: Provides the values for the SPM delay command i= n the SPM > + sequence > +- qcom,saw2-spm-ctl: The SPM control register Can we describe this as =93spm-enable=94, =93spm-inhibit-start-address=94= , =93spm-wakeup-cfg=94? Also, I=92m unclear why would we have a case that spm would be disabled= ? > +- qcom,name: The name with which a SPM device is identified by the p= ower > + management code. > + > +Optional properties > + > +- qcom,saw2-pmic-data0..7: Specify the pmic data value and the assoc= iated FTS > + (Fast Transient Switch) index to send the PMIC data to > +- qcom,vctl-port: The PVC (PMIC Virtual Channel) port used for chang= ing > + voltage > +- qcom,phase-port: The PVC port used for changing the number of phas= es > +- qcom,pfm-port: The PVC port used for enabling PWM/PFM modes > +- qcom,saw2-spm-cmd-wfi: The WFI command sequence > +- qcom,saw2-spm-cmd-ret: The Retention command sequence > +- qcom,saw2-spm-cmd-spc: The Standalone PC command sequence > +- qcom,saw2-spm-cmd-pc-no-rpm: The Power Collapse command sequence w= here APPS > + proc won't inform the RPM. > +- qcom,saw2-spm-cmd-pc: The Power Collapse command sequence. This se= quence may > + turn off other SoC components. > +- qcom,saw2-spm-cmd-gdhs: GDHS (Globally Distributed Head Switch) co= mmand > + sequence. This sequence will retain the memory but turn off the log= ic. > +- qcom,cpu-vctl-list: List of cpu node phandles, whose voltage the s= pm device > + can control. > +- qcom,vctl-timeout-us: The timeout value in microseconds to wait fo= r voltage to > + change after sending the voltage command to the PMIC. > +- > +Example: > + qcom,spm@f9089000 { > + compatible =3D "qcom,spm-v2"; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + reg =3D <0xf9089000 0x1000>; > + qcom,cpu =3D <&CPU0>; > + qcom,saw2-cfg =3D <0x1>; > + qcom,saw2-spm-dly=3D <0x20000400>; > + qcom,saw2-spm-ctl =3D <0x1>; > + qcom,saw2-spm-cmd-wfi =3D [03 0b 0f]; > + qcom,saw2-spm-cmd-spc =3D [00 20 50 80 60 70 10 92 > + a0 b0 03 68 70 3b 92 a0 b0 > + 82 2b 50 10 30 02 22 30 0f]; > + }; --=20 Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, host= ed by The Linux Foundation