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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e5e99e04sm93498145e9.11.2025.08.07.08.07.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Aug 2025 08:07:26 -0700 (PDT) Message-ID: <63ce3c8b-51a3-45a7-a40e-330839d7dbf3@linaro.org> Date: Thu, 7 Aug 2025 16:07:24 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 09/10] [RFT] arm64: dts: qcom: sm8250: extend CAMSS with new CSIPHY subdevices To: Neil Armstrong , Vladimir Zapolskiy , Krzysztof Kozlowski , Rob Herring , Bjorn Andersson , Konrad Dybcio Cc: Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org References: <20250612011531.2923701-1-vladimir.zapolskiy@linaro.org> <20250612011531.2923701-10-vladimir.zapolskiy@linaro.org> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 07/08/2025 15:17, Neil Armstrong wrote: >> >> https://lore.kernel.org/linux-media/20250711-b4-linux-next-25-03-13- >> dtsi-x1e80100-camss-v7-0-0bc5da82f526@linaro.org >> >> V2 of the CSIPHY above will incorporate feedback from Neil and >> yourself on adding endpoint@ to the PHY however I think we need to >> have a conversation about standards compliance at attaching two >> sensors to one CSIPHY without VCs or TDM. > > The PHY is able to setup 2 lanes as clock and connect 2 sensors over the > 5 lanes available, like for example: > - lane0: cam0 data0 > - lane1: cam0 data1 > - lane2: cam1 data0 > - lane3: cam1 clk > - lane4: cam0 clk > > Any lane mapping is compliant. There some Meta slides about that at: > https://www.edge-ai-vision.com/wp-content/uploads/2024/09/T2R10_Kumaran- > Ayyalluseshagiri-Viswanathan_Meta_2024.pdf slide 13 Hmm so that would require splitting the CSIPHY between two CSI decoders which I'm not sure would work on our hardware, perhaps yes, perhaps no, or routing both sensors into the one CSI decoder and then separating the data-streams either in the driver or in user-space. For such an esoteric setup I think my initial suggestion would be to push it into user-space, even assuming you have gotten the PHY to co-operate with having two simultaneous clock lanes per the above link. Looking at the PHY regs, I guess you can set the bits but obviously the analogue component of the PHY can only really operate from the one clock lane.... Interesting. --- bod