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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDIyMDE2OCBTYWx0ZWRfX3QZCZc/X/l0x d/FfzklzAlWWZ5wzJj71DS92X18r8mDFbtInZxgKgpdCi/pshjUpWhsXrA3ZlFFKamLqX0l9GEM PQ8UBznzqLo3ZF9TlH/ynivjbiSzVRfOoxeaQZ00XCKYfrCjRfiltsfQIv5lYHT9WUHmagGDjB2 xrKXnilFytF9YfZjSLzzdzGO6hiOF9mbOXPiHv9g7A4ig4KzvfT2C74yEiuxW9FGET31muz01h+ G7UZN94rDhBcNB4hIEIqOBYNP4ehHtP1TBAxSVy1YbRPZJfeLLbArRG1Qk+NU5lDbSl4KT0bOWF 40iHmN0vaRIiC5dzVl1dV5Gs9zfCMQlE0zttgpyf7/PZ0UZEBLZekaWnzQYck1n2KtdQbZ0CwTA 47ZSLbgkTGX/gBgbz0Ac5iHWSIuHDA== X-Authority-Analysis: v=2.4 cv=LMRrgZW9 c=1 sm=1 tr=0 ts=68f9c1b8 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=sRLNwhOJ/yCBC+ZuepprkA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=g-qGA7akq0XnR0fS_kUA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: Rdebd1aKHfVx-Zt_CMCtbpj0EpjfMRNo X-Proofpoint-ORIG-GUID: Rdebd1aKHfVx-Zt_CMCtbpj0EpjfMRNo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-22_08,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 phishscore=0 bulkscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510220168 On 10/23/2025 2:03 AM, Bjorn Andersson wrote: > On Wed, Oct 22, 2025 at 02:10:50PM +0530, Krishna Kurapati wrote: >> From: Wesley Cheng >> >> Add the base USB devicetree definitions for SM8750 platforms. The overall > > Please start your commit message with the problem description and leave > the description of the "solution" to later. > > If you replace "overall" with "SM8750" the second sentence is a good > start. > >> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY >> (rev. v8) and M31 eUSB2 PHY. The major difference for SM8750 is the > > "The major difference from previous SoCs is the..." > >> transition to using the M31 eUSB2 PHY compared to previous SoCs. >> >> Enable USB support on SM8750 MTP and QRD variants. SM8750 has a QMP combo >> PHY for the SSUSB path, and a M31 eUSB2 PHY for the HSUSB path. >> >> Signed-off-by: Wesley Cheng >> Suggested-by: Konrad Dybcio > > This means "Konrad suggested that I implement this patch". > >> [Konrad: Suggestion to flatten DT] > > This syntax is for "patch was originally authored by above, but "name" > changed it in so-and-so way". > > In other words, while the gesture of giving Konrad credit for his > suggestion during review is nice, you should omit the Suggested-by and > you should cover bigger things you changed since Wesley wrote the patch, > i.e. say: > > [krishna: Flattened dwc3 node] > My bad. Actually Wesley implemented the original patch. Konrad provided a diff to flatten it. I sent it. Let me rephrase the [] block as follows: [Konrad: Flattened the dwc3 node] Hope that would be clear. >> Signed-off-by: Krishna Kurapati >> --- >> arch/arm64/boot/dts/qcom/sm8750.dtsi | 158 +++++++++++++++++++++++++++ >> 1 file changed, 158 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> index a82d9867c7cb..d933c378bd8d 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> @@ -12,6 +12,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -2581,6 +2582,163 @@ data-pins { >> }; >> }; >> >> + usb_1_hsphy: phy@88e3000 { >> + compatible = "qcom,sm8750-m31-eusb2-phy"; >> + reg = <0x0 0x88e3000 0x0 0x29c>; >> + >> + clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>; >> + clock-names = "ref"; >> + >> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; >> + >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + usb_dp_qmpphy: phy@88e8000 { >> + compatible = "qcom,sm8750-qmp-usb3-dp-phy"; >> + reg = <0x0 0x088e8000 0x0 0x4000>; >> + >> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, >> + <&tcsrcc TCSR_USB3_CLKREF_EN>, >> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, >> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; >> + clock-names = "aux", >> + "ref", >> + "com_aux", >> + "usb3_pipe"; >> + >> + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, >> + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; >> + reset-names = "phy", >> + "common"; >> + >> + power-domains = <&gcc GCC_USB3_PHY_GDSC>; >> + >> + #clock-cells = <1>; >> + #phy-cells = <1>; >> + >> + orientation-switch; >> + >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + >> + usb_dp_qmpphy_out: endpoint { >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + >> + usb_dp_qmpphy_usb_ss_in: endpoint { >> + remote-endpoint = <&usb_1_dwc3_ss>; >> + }; >> + }; >> + >> + port@2 { >> + reg = <2>; >> + >> + usb_dp_qmpphy_dp_in: endpoint { >> + }; >> + }; >> + }; >> + }; >> + >> + usb_1: usb@a600000 { > > Commit message says there's a single USB controller, so why does it need > a _1 suffix? (Same with usb_1_hsphy above) > ACK. Will use just "usb" as node name. Regards, Krishna,