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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id f20-20020a193814000000b004b55ca70844sm1003547lfa.175.2022.12.14.17.08.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Dec 2022 17:08:14 -0800 (PST) Message-ID: <658da2cf-1e1a-af27-b085-edf0887b8dae@linaro.org> Date: Thu, 15 Dec 2022 03:08:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.1 Subject: Re: [RFC PATCH 3/6] drm/msm/dpu1: Wire up DSC mask for active CTL configuration Content-Language: en-GB To: Marijn Suijten , phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Vinod Koul , ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Sean Paul , David Airlie , Daniel Vetter , Stephen Boyd , Bjorn Andersson , Jessica Zhang , =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= , Kuogee Hsieh , Jani Nikula , sunliming , Sam Ravnborg , Haowen Bai , Konrad Dybcio , Loic Poulain , Vinod Polimera , Douglas Anderson , Vladimir Lypak , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20221213232207.113607-1-marijn.suijten@somainline.org> <20221213232207.113607-4-marijn.suijten@somainline.org> <184d22f1-7ed1-4a67-1c25-9fafeb94db83@linaro.org> <20221214193026.dv2fuubysctcvlkg@SoMainline.org> From: Dmitry Baryshkov In-Reply-To: <20221214193026.dv2fuubysctcvlkg@SoMainline.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 14/12/2022 21:30, Marijn Suijten wrote: > On 2022-12-14 20:43:29, Dmitry Baryshkov wrote: >> On 14/12/2022 01:22, Marijn Suijten wrote: >>> Active CTLs have to configure what DSC block(s) have to be enabled, and >>> what DSC block(s) have to be flushed; this value was initialized to zero >>> resulting in the necessary register writes to never happen (or would >>> write zero otherwise). This seems to have gotten lost in the DSC v4->v5 >>> series while refactoring how the combination with merge_3d was handled. >>> >>> Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder") >>> Signed-off-by: Marijn Suijten >>> --- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 1 + >>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 1 + >>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 ++ >>> 3 files changed, 4 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c >>> index ae28b2b93e69..35791f93c33d 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c >>> @@ -61,6 +61,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( >>> intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; >>> intf_cfg.stream_sel = cmd_enc->stream_sel; >>> intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); >>> + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); >>> ctl->ops.setup_intf_cfg(ctl, &intf_cfg); >>> >>> /* setup which pp blk will connect to this intf */ >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >>> index 0f71e8fe7be7..9ee3a7306a5f 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >>> @@ -274,6 +274,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( >>> intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; >>> intf_cfg.stream_sel = 0; /* Don't care value for video mode */ >>> intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); >>> + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); >>> if (phys_enc->hw_pp->merge_3d) >>> intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; >>> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c >>> index 7cbcef6efe17..92ddf9995b37 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c >>> @@ -209,6 +209,7 @@ static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc) >>> >>> intf_cfg.intf = DPU_NONE; >>> intf_cfg.wb = hw_wb->idx; >>> + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); >> >> We usually don't have DSC with the writeback, don't we? > > I am unsure so ended up adding them in writeback regardless. Downstream > uses a separate callback to process intf_cfg.dsc instead of going > through setup_intf_cfg(). > > To prevent these from being missed again (in the case of copy&paste), > how about instead having some function that sets up intf_cfg with these > default values from a phys_enc? That way most of this remains oblivious > to the caller. I'm not sure this is possible. E.g. intf_cfg.dsc should not be set for the WB. > > On the same note, that callback on non-DPU_CTL_ACTIVE_CFG hardware > doesn't use the intf_cfg.dsc member anyway, but it was again added to > keep the blocks somewhat consistent (in case it ever becomes used?). > >>> if (mode_3d && hw_pp && hw_pp->merge_3d) >>> intf_cfg.merge_3d = hw_pp->merge_3d->idx; >>> @@ -230,6 +231,7 @@ static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc) >>> intf_cfg.wb = hw_wb->idx; >>> intf_cfg.mode_3d = >>> dpu_encoder_helper_get_3d_blend_mode(phys_enc); >>> + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); >>> phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); >>> } >>> } > > - Marijn -- With best wishes Dmitry