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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: QP7qNxIC6Y6waK0H8_LABY-XqZ3q1VkR X-Authority-Analysis: v=2.4 cv=LegxKzfi c=1 sm=1 tr=0 ts=69aaa0f9 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=uL+hpB4jSAN/g3a/thif0w==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=_nDl3K6yXJEX041QHmYA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA2MDA5MSBTYWx0ZWRfX3/HlHnL8LDRA ISe4el3gNnL/IsPybAg894Lt4nuYX9o9GfVhT/mcsGGk1rfSQjXeXwX7rnBQ14nkmcs0CrtT2YI 6dFhqsVJ+QDPjFHSeC89/0AsHxOnXAQchS/gXn8JUXmbvaJcTfPF921E+Ed32kqyE0fcw3VAm4Z RrbnrjOzn34BGLvLHB6CxUbNQrI25TM3VJ+mN8rBFZdAEaF5qwo6WNGvtQ88C9prWLaBX2+SjJe rT6aZsxFhCfiGCst2P6mXIplbGdvoxPbzuaPREic7JyXCyDx8dZsNMAytaNok0aIO6w0wY8TDXb 3qvqvAFdHtjwNqs2Y4qrF7XQfCBqNZah7YFs9Tgy0eB/9RHqw2Hf2bW5DvjAq31ibC8vWsJ91E/ dd8fJyGN6hQf0b+WPQU4r9ddgBDXyIEQLAyzh+zyDGRu0QR+izpF77EVaS5CgN7Vy1/xqD3aSgE ma0vXyUsz7A1/MW65AA== X-Proofpoint-GUID: QP7qNxIC6Y6waK0H8_LABY-XqZ3q1VkR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-06_03,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 bulkscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603060091 On 3/5/2026 4:10 PM, Taniya Das wrote: > From: Konrad Dybcio > > Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this > is simply a separate block housing the GX GDSC) nodes, required to > power up the graphics-related hardware. > > Make use of it by enabling the associated IOMMU as well. The GPU itself > needs some more work and will be enabled later. > > Reviewed-by: Abel Vesa > Signed-off-by: Konrad Dybcio > Co-developed-by: Taniya Das > Signed-off-by: Taniya Das > --- > arch/arm64/boot/dts/qcom/sm8750.dtsi | 68 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 68 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi > index f56b1f889b857a28859910f5c4465c8ce3473b00..0e7a343297e3f5d7a8189f50726dc6279078c21c 100644 > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi > @@ -4,7 +4,9 @@ > */ > > #include > +#include > #include > +#include > #include > #include > #include > @@ -3001,6 +3003,34 @@ videocc: clock-controller@aaf0000 { > #power-domain-cells = <1>; > }; > > + gxclkctl: clock-controller@3d64000 { > + compatible = "qcom,sm8750-gxclkctl"; > + reg = <0x0 0x03d64000 0x0 0x6000>; > + > + power-domains = <&rpmhpd RPMHPD_GFX>, > + <&rpmhpd RPMHPD_GMXC>, > + <&gpucc GPU_CC_CX_GDSC>; > + > + #power-domain-cells = <1>; > + }; > + > + gpucc: clock-controller@3d90000 { > + compatible = "qcom,sm8750-gpucc"; > + reg = <0x0 0x03d90000 0x0 0x9800>; > + > + clocks = <&bi_tcxo_div2>, > + <&gcc GCC_GPU_GPLL0_CLK_SRC>, > + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; > + > + power-domains = <&rpmhpd RPMHPD_MX>, > + <&rpmhpd RPMHPD_CX>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,sm8750-pdc", "qcom,pdc"; > reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; > @@ -4515,6 +4545,44 @@ tpdm_swao_out: endpoint { > }; > }; > > + adreno_smmu: iommu@3da0000 { Should we move this node right after the gpucc node to sort based on address? -Akhil. > + compatible = "qcom,sm8750-smmu-500", "qcom,adreno-smmu", > + "qcom,smmu-500", "arm,mmu-500"; > + reg = <0x0 0x03da0000 0x0 0x40000>; > + #iommu-cells = <2>; > + #global-interrupts = <1>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; > + clock-names = "hlos"; > + power-domains = <&gpucc GPU_CC_CX_GDSC>; > + dma-coherent; > + }; > + > apps_smmu: iommu@15000000 { > compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > reg = <0x0 0x15000000 0x0 0x100000>; >