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From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	Rob Clark <robin.clark@oss.qualcomm.com>,
	Sean Paul <sean@poorly.run>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Dmitry Baryshkov <lumag@kernel.org>,
	Abhinav Kumar <abhinav.kumar@linux.dev>,
	Jessica Zhang <jesszhan0024@gmail.com>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Antonino Maniscalco <antomani103@gmail.com>,
	Connor Abbott <cwabbott0@gmail.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>
Subject: Re: [PATCH v2 10/17] drm/msm/a6xx: Update HFI definitions
Date: Tue, 31 Mar 2026 01:57:26 +0530	[thread overview]
Message-ID: <67cca0c6-669c-4dcf-be3f-76fc46d1e59f@oss.qualcomm.com> (raw)
In-Reply-To: <3465929e-262f-407e-bc3d-7564787bce3d@oss.qualcomm.com>

On 3/30/2026 4:45 PM, Konrad Dybcio wrote:
> On 3/27/26 1:13 AM, Akhil P Oommen wrote:
>> Update the HFI definitions to support additional GMU based power
>> features.
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
> 
> Whether you want to proceed with bitfields or not:
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Thanks. I still feel it is bitfield layout is a 'bit' complicated.

I did an experiment:

#include <stdio.h>
#include <stdint.h>
#include <stddef.h>

struct packed_u8 {
        uint16_t mitigation_time;
        uint8_t current_rating    : 6;
        uint8_t num_phases        : 6;
        uint8_t path_notification : 1;
        uint8_t extra_features    : 3;
} __packed;


void main() {

        struct packed_u8 data = {
                 .mitigation_time  = 0xffff,
                 .current_rating   = 0x3f,  /* all 6 bits set */
                 .num_phases       = 0x3f,
                 .path_notification = 1,
                 .extra_features   = 0x7,
         };

        printf("Akhil 0x%x\n", *((uint32_t *) &data));
}

The output I got in Kaanapali is: Akhil 0x7f3fffff

This means that the compiler inserted a padding between current_rating
and num_phases.

-Akhil.

> 
> Konrad


  reply	other threads:[~2026-03-30 20:27 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-27  0:13 [PATCH v2 00/17] drm/msm: A8xx Support - Batch 2 Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 01/17] drm/msm/a6xx: Use barriers while updating HFI Q headers Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 02/17] drm/msm/a8xx: Fix the ticks used in submit traces Akhil P Oommen
2026-03-27 11:37   ` Konrad Dybcio
2026-03-30 20:58     ` Akhil P Oommen
2026-03-31  8:23       ` Konrad Dybcio
2026-03-27  0:13 ` [PATCH v2 03/17] drm/msm/a6xx: Switch to preemption safe AO counter Akhil P Oommen
2026-03-27 11:32   ` Konrad Dybcio
2026-03-30 20:51     ` Akhil P Oommen
2026-03-30 21:34       ` Rob Clark
2026-03-27  0:13 ` [PATCH v2 04/17] drm/msm/a6xx: Correct OOB usage Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 05/17] drm/msm/adreno: Implement gx_is_on() for A8x Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 06/17] drm/msm/a6xx: Fix gpu init from secure world Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 07/17] drm/msm/a6xx: Add support for Debug HFI Q Akhil P Oommen
2026-03-27 10:34   ` Konrad Dybcio
2026-03-27  0:13 ` [PATCH v2 08/17] drm/msm/adreno: Coredump on GPU/GMU init failures Akhil P Oommen
2026-03-27 11:35   ` Konrad Dybcio
2026-03-30 20:53     ` Akhil P Oommen
2026-03-30 19:51   ` Rob Clark
2026-03-31 18:05     ` Akhil P Oommen
2026-03-31 18:28       ` Rob Clark
2026-03-27  0:13 ` [PATCH v2 09/17] drm/msm/a6xx: Use packed structs for HFI Akhil P Oommen
2026-03-27  0:13 ` [PATCH v2 10/17] drm/msm/a6xx: Update HFI definitions Akhil P Oommen
2026-03-30 11:15   ` Konrad Dybcio
2026-03-30 20:27     ` Akhil P Oommen [this message]
2026-03-31  8:22       ` Konrad Dybcio
2026-03-31 17:44         ` Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 11/17] drm/msm/a8xx: Add SKU table for A840 Akhil P Oommen
2026-03-27 11:14   ` Konrad Dybcio
2026-03-30 20:35     ` Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 12/17] drm/msm/a6xx: Add soft fuse detection support Akhil P Oommen
2026-03-27 11:16   ` Konrad Dybcio
2026-03-30 20:36     ` Akhil P Oommen
2026-04-11  2:19   ` Jie Gan
2026-03-27  0:14 ` [PATCH v2 13/17] drm/msm/a6xx: Add SKU detection support for X2-85 Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 14/17] drm/msm/a8xx: Implement IFPC support for A840 Akhil P Oommen
2026-03-27 11:07   ` Konrad Dybcio
2026-03-30 20:34     ` Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 15/17] drm/msm/a8xx: Preemption " Akhil P Oommen
2026-04-11  2:22   ` Jie Gan
2026-04-11 13:56     ` Rob Clark
2026-04-11 14:45       ` David Laight
2026-03-27  0:14 ` [PATCH v2 16/17] drm/msm/a6xx: Enable Preemption on X2-85 Akhil P Oommen
2026-03-27  0:14 ` [PATCH v2 17/17] drm/msm/adreno: Expose a PARAM to check AQE support Akhil P Oommen
2026-03-27 11:19   ` Konrad Dybcio

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