From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Praveenkumar I <quic_ipkumar@quicinc.com>,
agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, amitk@kernel.org,
thara.gopinath@gmail.com, rafael@kernel.org,
daniel.lezcano@linaro.org, rui.zhang@intel.com,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, linux-arm-msm@vger.kernel.org,
linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: quic_varada@quicinc.com
Subject: Re: [PATCH 1/6] dt-bindings: thermal: tsens: Add nvmem cells for calibration data
Date: Thu, 13 Jul 2023 13:38:37 +0200 [thread overview]
Message-ID: <684ce378-a697-a352-eba7-c8f3ad62d8e4@linaro.org> (raw)
In-Reply-To: <1b050086-07c5-add6-6002-d7368d532566@quicinc.com>
On 11/07/2023 16:13, Praveenkumar I wrote:
>>>>> - const: calib
>>>>> @@ -205,6 +209,24 @@ properties:
>>>>> - const: s9_p2_backup
>>>>> - const: s10_p1_backup
>>>>> - const: s10_p2_backup
>>>>> + - items:
>>>>> + - const: mode
>>>>> + - const: base0
>>>>> + - const: base1
>>>>> + - const: s0_offset
>>>>> + - const: s3_offset
>>>>> + - const: s4_offset
>>>>> + - const: s5_offset
>>>>> + - const: s6_offset
>>>>> + - const: s7_offset
>>>>> + - const: s8_offset
>>>>> + - const: s9_offset
>>>>> + - const: s10_offset
>>>>> + - const: s11_offset
>>>>> + - const: s12_offset
>>>>> + - const: s13_offset
>>>>> + - const: s14_offset
>>>>> + - const: s15_offset
>>>> Don't introduce new naming style. Existing uses s[0-9]+, without offset
>>>> suffix. Why this should be different?
>>> As I mentioned above, s[0-9]+_p1 / s[0-9]+p2 is for TSENS V1. TSENS V2
>>> QFPROM layout is different from the existing one.
>> I know, I did not write about p1/p2.
>>
>>> I would like to add mode, base0, base1 and 16 patterns
>>> '^s[0-15]+_offset$'. But DT binding check is failing in oneOf/ anyOf
>>> condintion.
>> This does not explain why you need different style - this "offset" suffix.
> In QFPROM, the BIT field names are s0_offset, s3_offset to s15_offset.
> s1_offset and s2_offset not present in IPQ5332.
> Hence used the same "offset" suffix here. May I know in this case, which
> nvmem-cells-names you are suggesting to use?
"Existing uses s[0-9]+"
so s[0-9]+
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-07-13 11:38 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-10 10:37 [PATCH 0/6] Add IPQ5332 TSENS support Praveenkumar I
2023-07-10 10:37 ` [PATCH 1/6] dt-bindings: thermal: tsens: Add nvmem cells for calibration data Praveenkumar I
2023-07-10 20:10 ` Krzysztof Kozlowski
2023-07-11 9:39 ` Praveenkumar I
2023-07-11 9:52 ` Krzysztof Kozlowski
2023-07-11 14:13 ` Praveenkumar I
2023-07-13 11:38 ` Krzysztof Kozlowski [this message]
2023-07-10 10:37 ` [PATCH 2/6] thermal/drivers/tsens: Add TSENS enable and calibration support for V2 Praveenkumar I
2023-07-10 11:19 ` Dmitry Baryshkov
2023-07-10 11:22 ` Dmitry Baryshkov
2023-07-10 13:24 ` Praveenkumar I
2023-07-10 13:22 ` Praveenkumar I
2023-07-10 15:02 ` Dmitry Baryshkov
2023-07-11 9:19 ` Praveenkumar I
2023-07-10 10:37 ` [PATCH 3/6] dt-bindings: thermal: tsens: Add ipq5332 compatible Praveenkumar I
2023-07-10 20:06 ` Krzysztof Kozlowski
2023-07-11 9:24 ` Praveenkumar I
2023-07-10 10:37 ` [PATCH 4/6] arm64: dts: qcom: ipq5332: Add tsens node Praveenkumar I
2023-07-10 11:21 ` Dmitry Baryshkov
2023-07-10 13:25 ` Praveenkumar I
2023-07-10 20:07 ` Krzysztof Kozlowski
2023-07-11 9:27 ` Praveenkumar I
2023-07-10 10:37 ` [PATCH 5/6] arm64: dts: qcom: ipq5332: Add thermal zone nodes Praveenkumar I
2023-07-10 11:23 ` Dmitry Baryshkov
2023-07-10 12:14 ` Konrad Dybcio
2023-07-10 13:34 ` Praveenkumar I
2023-07-10 13:54 ` Praveenkumar I
2023-07-10 13:30 ` Praveenkumar I
2023-07-10 10:37 ` [PATCH 6/6] thermal/drivers/tsens: Add IPQ5332 support Praveenkumar I
2023-07-10 11:24 ` Dmitry Baryshkov
2023-07-10 13:47 ` Praveenkumar I
2023-07-10 15:03 ` Dmitry Baryshkov
2023-07-11 9:20 ` Praveenkumar I
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