From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B208EC433B4 for ; Mon, 3 May 2021 17:08:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 892876100A for ; Mon, 3 May 2021 17:08:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232311AbhECRIv (ORCPT ); Mon, 3 May 2021 13:08:51 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:49177 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234940AbhECRDO (ORCPT ); Mon, 3 May 2021 13:03:14 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1620061339; h=Message-ID: References: In-Reply-To: Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=IHgBKszPDfI9boQsp7/GZvBwgpgeZ+KI0dR7l18CnEY=; b=kvtvcYf/sQJhNDA05tYpTh2WAVs5udfZsdgSX+a1DBPgiWUI8P9xIXuEMWd3GBdtOa3pCgF4 i+8Gj66GSgdCuRzcn8YNLKPaA7IgqFwd3UfpQOQt+R3/p1UCU9q6h0g7fDoiO/0KzeOE6DPb Y8zwAm+w/w5PU0w0tpDHRHwM/38= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n06.prod.us-east-1.postgun.com with SMTP id 60902c748166b7eff7b9ed8d (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 03 May 2021 17:01:40 GMT Sender: bbhatt=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 5962EC28D92; Mon, 3 May 2021 17:01:39 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: bbhatt) by smtp.codeaurora.org (Postfix) with ESMTPSA id 99167C25359; Mon, 3 May 2021 17:01:37 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Mon, 03 May 2021 10:01:37 -0700 From: Bhaumik Bhatt To: Loic Poulain Cc: mani@kernel.org, hemantk@codeaurora.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v2] bus: mhi: core: Fix power down latency Organization: Qualcomm Innovation Center, Inc. Reply-To: bbhatt@codeaurora.org Mail-Reply-To: bbhatt@codeaurora.org In-Reply-To: <1620029090-8975-1-git-send-email-loic.poulain@linaro.org> References: <1620029090-8975-1-git-send-email-loic.poulain@linaro.org> Message-ID: <6a871b31f4f5c7ab8f12b75eed9861d3@codeaurora.org> X-Sender: bbhatt@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2021-05-03 01:04 AM, Loic Poulain wrote: > On graceful power-down/disable transition, when an MHI reset is > performed, the MHI device loses its context, including interrupt > configuration. However, the current implementation is waiting for > event(irq) driven state change to confirm reset has been completed, > which never happens, and causes reset timeout, leading to unexpected > high latency of the mhi_power_down procedure (up to 45 seconds). > > Fix that by moving to the recently introduced poll_reg_field method, > waiting for the reset bit to be cleared, in the same way as the > power_on procedure. > > Fixes: a6e2e3522f29 ("bus: mhi: core: Add support for PM state > transitions") > Signed-off-by: Loic Poulain > --- Reviewed-by: Bhaumik Bhatt > drivers/bus/mhi/core/pm.c | 18 +++++------------- > 1 file changed, 5 insertions(+), 13 deletions(-) > > diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c > index e2e59a3..704a5e2 100644 > --- a/drivers/bus/mhi/core/pm.c > +++ b/drivers/bus/mhi/core/pm.c > @@ -465,23 +465,15 @@ static void mhi_pm_disable_transition(struct > mhi_controller *mhi_cntrl) > > /* Trigger MHI RESET so that the device will not access host memory > */ > if (!MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) { > - u32 in_reset = -1; > - unsigned long timeout = msecs_to_jiffies(mhi_cntrl->timeout_ms); > - > dev_dbg(dev, "Triggering MHI Reset in device\n"); > mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET); > > /* Wait for the reset bit to be cleared by the device */ > - ret = wait_event_timeout(mhi_cntrl->state_event, > - mhi_read_reg_field(mhi_cntrl, > - mhi_cntrl->regs, > - MHICTRL, > - MHICTRL_RESET_MASK, > - MHICTRL_RESET_SHIFT, > - &in_reset) || > - !in_reset, timeout); > - if (!ret || in_reset) > - dev_err(dev, "Device failed to exit MHI Reset state\n"); > + ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL, > + MHICTRL_RESET_MASK, MHICTRL_RESET_SHIFT, 0, > + 25000); > + if (ret) > + dev_err(dev, "Device failed to clear MHI Reset\n"); > > /* > * Device will clear BHI_INTVEC as a part of RESET processing, Thanks, Bhaumik --- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project