From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBE0EC7EE2A for ; Thu, 1 Jun 2023 13:29:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233881AbjFAN3Q (ORCPT ); Thu, 1 Jun 2023 09:29:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234004AbjFAN3A (ORCPT ); Thu, 1 Jun 2023 09:29:00 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4EA0E1B8; Thu, 1 Jun 2023 06:28:29 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2643AC14; Thu, 1 Jun 2023 06:29:14 -0700 (PDT) Received: from [10.57.22.125] (unknown [10.57.22.125]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 22A703F7D8; Thu, 1 Jun 2023 06:28:26 -0700 (PDT) Message-ID: <6be47f1a-16ca-76ca-b133-ee453c261c21@arm.com> Date: Thu, 1 Jun 2023 14:28:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.11.1 Subject: Re: [PATCH v4 08/11] coresight-tpdm: Add nodes to configure pattern match output To: Tao Zhang , Mathieu Poirier , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski Cc: Jinlong Mao , Leo Yan , Greg Kroah-Hartman , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , linux-arm-msm@vger.kernel.org, andersson@kernel.org References: <1682586037-25973-1-git-send-email-quic_taozha@quicinc.com> <1682586037-25973-9-git-send-email-quic_taozha@quicinc.com> From: Suzuki K Poulose In-Reply-To: <1682586037-25973-9-git-send-email-quic_taozha@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 27/04/2023 10:00, Tao Zhang wrote: > Add nodes to configure trigger pattern and trigger pattern mask. > Each DSB subunit TPDM has maximum of n(n<7) XPR registers to > configure trigger pattern match output. Eight 32 bit registers > providing DSB interface trigger output pattern match comparison. > And each DSB subunit TPDM has maximum of m(m<7) XPMR registers to > configure trigger pattern mask match output. Eight 32 bit > registers providing DSB interface trigger output pattern match > mask. > > Signed-off-by: Tao Zhang > --- > .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 30 ++++++++ > drivers/hwtracing/coresight/coresight-tpdm.c | 85 ++++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpdm.h | 8 ++ > 3 files changed, 123 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > index a57f000..c04c735 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > @@ -92,3 +92,33 @@ Description: > : Start EDCMR register number > : End EDCMR register number > : The value need to be written > + > +What: /sys/bus/coresight/devices//dsb_trig_patt_val > +Date: March 2023 > +KernelVersion 6.3 > +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) > +Description: > + (Write) Set the trigger pattern value of DSB tpdm. > + Read the trigger pattern value of DSB tpdm. > + > + Expected format is the following: > + > + > + Where: > + : Index number of XPR register, the range is 0 to 7 > + : The value need to be written I assume the values written to the registers are not special and doesn't have meaning and thus need not be documented ? > + > +What: /sys/bus/coresight/devices//dsb_trig_patt_mask > +Date: March 2023 > +KernelVersion 6.3 Same as the previous one, 6.5 please > +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) > +Description: > + (Write) Set the trigger pattern mask of DSB tpdm. > + Read the trigger pattern mask of DSB tpdm. > + > + Expected format is the following: > + > + > + Where: > + : Index number of XPMR register, the range is 0 to 7 > + : The value need to be written > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index a40e458..9387bdf 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -89,6 +89,13 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) > writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], > drvdata->base + TPDM_DSB_EDCMR(i)); > > + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { Same as the previous, can we safely assume that write to these registers won't trigger an Error if not impelemented ? > + writel_relaxed(drvdata->dsb->trig_patt_val[i], > + drvdata->base + TPDM_DSB_XPR(i)); > + writel_relaxed(drvdata->dsb->trig_patt_mask[i], > + drvdata->base + TPDM_DSB_XPMR(i)); > + } > + > val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); > /* Set trigger timestamp */ > if (drvdata->dsb->trig_ts) > @@ -444,6 +451,82 @@ static ssize_t dsb_edge_ctrl_mask_store(struct device *dev, > } > static DEVICE_ATTR_RW(dsb_edge_ctrl_mask); > > +static ssize_t dsb_trig_patt_val_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); > + ssize_t size = 0; > + int i = 0; > + > + spin_lock(&drvdata->spinlock); > + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { > + size += sysfs_emit_at(buf, size, > + "Index: 0x%x Value: 0x%x\n", i, > + drvdata->dsb->trig_patt_val[i]); Please detect the return of 0 and break. Same below. > + } > + spin_unlock(&drvdata->spinlock); > + return size; > +} > + > +static ssize_t dsb_trig_patt_val_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long index, val; > + > + if (sscanf(buf, "%lx %lx", &index, &val) != 2) > + return -EINVAL; > + if (index >= TPDM_DSB_MAX_PATT) > + return -EPERM; > + > + spin_lock(&drvdata->spinlock); > + drvdata->dsb->trig_patt_val[index] = val; > + spin_unlock(&drvdata->spinlock); > + return size; > +} > +static DEVICE_ATTR_RW(dsb_trig_patt_val); > + > +static ssize_t dsb_trig_patt_mask_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); > + ssize_t size = 0; > + int i = 0; > + > + spin_lock(&drvdata->spinlock); > + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { > + size += sysfs_emit_at(buf, size, > + "Index: 0x%x Value: 0x%x\n", i, > + drvdata->dsb->trig_patt_mask[i]); > + } > + spin_unlock(&drvdata->spinlock); > + return size; Suzuki