Re: [PATCH v1 2/3] drm/msm/adreno: Add support for X185 GPU

Akhil P Oommen
2024-06-26T20:49:31Z

On Mon, Jun 24, 2024 at 07:28:06AM -0700, Rob Clark wrote:
> On Mon, Jun 24, 2024 at 7:25 AM Rob Clark <robdclark@gmail.com> wrote:
> >
> > On Sun, Jun 23, 2024 at 4:08 AM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> > >
> > > Add support in drm/msm driver for the Adreno X185 gpu found in
> > > Snapdragon X1 Elite chipset.
> > >
> > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> > > ---
> > >
> > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++----
> > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++----
> > > drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++
> > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++
> > > 4 files changed, 36 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > > index 0e3dfd4c2bc8..168a4bddfaf2 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > > @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
> > > */
> > > gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);
> > >
> > > + if (adreno_is_x185(adreno_gpu)) {
> > > + chipid = 0x7050001;
> > > /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */
> > > - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) {
> > > + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) {
> > > /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */
> > > chipid = FIELD_PREP(GENMASK(31, 24), 0x7);
> > >
> > > @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
> > > if (!pri_count)
> > > return -EINVAL;
> > >
> > > - sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
> > > - if (IS_ERR(sec))
> > > - return PTR_ERR(sec);
> > > + /*
> > > + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back
> > > + * to regular mx rail if it is missing
> > > + */
> > > + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count);
> > > + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) {
> > > + return -EPROBE_DEFER;
> > > + } else if (IS_ERR(sec)) {
> > > + sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
> > > + if (IS_ERR(sec))
> > > + return PTR_ERR(sec);
> > > + }
> > >
> > > sec_count >>= 1;
> > > if (!sec_count)
> > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > index 973872ad0474..97837f7f2a40 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > @@ -1319,9 +1319,7 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> > > count = ARRAY_SIZE(a660_protect);
> > > count_max = 48;
> > > BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48);
> > > - } else if (adreno_is_a730(adreno_gpu) ||
> > > - adreno_is_a740(adreno_gpu) ||
> > > - adreno_is_a750(adreno_gpu)) {
> > > + } else if (adreno_is_a7xx(adreno_gpu)) {
> > > regs = a730_protect;
> > > count = ARRAY_SIZE(a730_protect);
> > > count_max = 48;
> > > @@ -1891,7 +1889,7 @@ static int hw_init(struct msm_gpu *gpu)
> > > gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1);
> > >
> > > /* Set weights for bicubic filtering */
> > > - if (adreno_is_a650_family(adreno_gpu)) {
> > > + if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) {
> > > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
> > > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
> > > 0x3fe05ff4);
> > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > index c3703a51287b..139c7d828749 100644
> > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > @@ -568,6 +568,20 @@ static const struct adreno_info gpulist[] = {
> > > .zapfw = "a740_zap.mdt",
> > > .hwcg = a740_hwcg,
> > > .address_space_size = SZ_16G,
> > > + }, {
> > > + .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */
> > > + .family = ADRENO_7XX_GEN2,
> > > + .fw = {
> > > + [ADRENO_FW_SQE] = "gen70500_sqe.fw",
> > > + [ADRENO_FW_GMU] = "gen70500_gmu.bin",
> > > + },
> > > + .gmem = 3 * SZ_1M,
> > > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> > > + ADRENO_QUIRK_HAS_HW_APRIV,
> > > + .init = a6xx_gpu_init,
> > > + .hwcg = a740_hwcg,
> > > + .address_space_size = SZ_16G,
> >
> > I'm kinda thinking we should drop the address_space_size and add
> > instead ADRENO_QUIRK_4G or something along those lines, since there
> > are devices with 32 or 64G
>
> or alternatively put in a correct address_space_size (I guess 2^^48 or 2^^56 ?)

Although I don't see any reason why the end address couldn't be the
'ttbr0/1 split address', we can keep 256GB as AS size for now. I will
check this further and see if we can have a general logic for non-a630_family.

-Akhil

>
> BR,
> -R
>
> > (a690 is incorrect in this way too)
> >
> > BR,
> > -R
> >
> > > }, {
> > > .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
> > > .family = ADRENO_7XX_GEN3,
> > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > index 77526892eb8c..d9ea8e0f6ad5 100644
> > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > @@ -448,6 +448,11 @@ static inline int adreno_is_a750(struct adreno_gpu *gpu)
> > > return gpu->info->chip_ids[0] == 0x43051401;
> > > }
> > >
> > > +static inline int adreno_is_x185(struct adreno_gpu *gpu)
> > > +{
> > > + return gpu->info->chip_ids[0] == 0x43050c01;
> > > +}
> > > +
> > > static inline int adreno_is_a740_family(struct adreno_gpu *gpu)
> > > {
> > > if (WARN_ON_ONCE(!gpu->info))
> > > --
> > > 2.45.1
> > >