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Wed, 08 Apr 2026 02:22:25 -0700 (PDT) X-Received: by 2002:a05:6a20:432b:b0:398:92ef:1d95 with SMTP id adf61e73a8af0-39f2ee70addmr21171879637.21.1775640144653; Wed, 08 Apr 2026 02:22:24 -0700 (PDT) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c76c659bedesm17266512a12.30.2026.04.08.02.22.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Apr 2026 02:22:24 -0700 (PDT) Message-ID: <6c48fed6-27df-449b-9e43-00a68e45b9ba@oss.qualcomm.com> Date: Wed, 8 Apr 2026 14:52:18 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] bus: mhi: host: Update the Time sync logic to read 64 bit register value To: Konrad Dybcio , Manivannan Sadhasivam , Richard Cochran Cc: mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, taniya.das@oss.qualcomm.com, imran.shaik@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com References: <20250818-tsc_time_sync-v1-0-2747710693ba@oss.qualcomm.com> <20250818-tsc_time_sync-v1-4-2747710693ba@oss.qualcomm.com> <16698a59-1a2f-4816-98fe-56b125be669b@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <16698a59-1a2f-4816-98fe-56b125be669b@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: by1LhY4aEn3scq0qZ_BZacZarc0yjoru X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA4MDA4NSBTYWx0ZWRfX8BE88M7TWzOV u8lqKayyKQTnSYU7GqFcRHtuyAcDs1yQ1tkFhG7m3rcJoRmbcq8PkT/bpjpemWLw4BSYFiVys7i VaedWrHZGCfYlqJVW+RENyTNeAhTkf7DDktVLeEXSjKmKjrmO2wC9rrun0amDu708Tr7Sl9qgHB 4XJFgHHUg+2o+vTvxNJqdLAz7922zBF0R4IoB1KNvk03RFTC6eER/wVHmNdKHa3LuSBcIhXqAjm om+0TkFQIvZ0iZ/BanXKs4IUnL/joFCTXYM/zY0DnVY20p0UfFs4/tddx2zkkxhyBgOb+YXITyp gbY+E43XUFQTv+DehfauLIzTVLxkM84AlF8bSCJVUEg8A9W9Zl3sGjrOnozZMvke6tKO2pBArhu vb6/OxaJnFuJ3WykzoNEEcgbnM9ttE9RLNywKr5Gjj1OZFzVra/ezhN0MDM6EMdDGTMeKHAD4jS WbC/hD9ZwQrazLpztBQ== X-Authority-Analysis: v=2.4 cv=GN041ONK c=1 sm=1 tr=0 ts=69d61e51 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=cgR8ezsCSdHxW5zDJ1AA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: by1LhY4aEn3scq0qZ_BZacZarc0yjoru X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-08_03,2026-04-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 suspectscore=0 clxscore=1015 spamscore=0 adultscore=0 bulkscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080085 On 9/2/2025 2:44 PM, Konrad Dybcio wrote: > On 8/18/25 8:55 AM, Krishna Chaitanya Chundru wrote: >> Instead of reading low and high of the mhi registers twice use 64 bit >> register value to avoid any time penality. >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/bus/mhi/host/main.c | 19 +++++++++++++++---- >> 1 file changed, 15 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c >> index b7ceeb7261b708d46572d1f68dc277b6e1186b6e..f628198218ef9dc760bbfc3ec496603d1a45dfc1 100644 >> --- a/drivers/bus/mhi/host/main.c >> +++ b/drivers/bus/mhi/host/main.c >> @@ -1719,6 +1719,7 @@ static int mhi_get_remote_time(struct mhi_controller *mhi_cntrl, struct mhi_time >> struct mhi_timesync_info *time) >> { >> struct device *dev = &mhi_cntrl->mhi_dev->dev; >> + u64 val = U64_MAX; >> int ret, i; >> >> if (!mhi_tsync && !mhi_tsync->time_reg) { >> @@ -1756,15 +1757,25 @@ static int mhi_get_remote_time(struct mhi_controller *mhi_cntrl, struct mhi_time >> * transition to L0. >> */ >> for (i = 0; i < MHI_NUM_BACK_TO_BACK_READS; i++) { >> - ret = mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg, >> - TSC_TIMESYNC_TIME_LOW_OFFSET, &time->t_dev_lo); >> + if (mhi_cntrl->read_reg64) { >> + ret = mhi_read_reg64(mhi_cntrl, mhi_tsync->time_reg, >> + TSC_TIMESYNC_TIME_LOW_OFFSET, &val); > Since you're passing mhi_cntrl to the read_reg64 function anyway, > perhaps this could remove some verbosity: Hi Konrad, Sorry for late reply, in pci_generic patch we are defining read_reg64 only if readq is defined in the system.  As per your suggesting if we go define mhi_read_reg64 always, we need to have #ifdef inside the mhi_read_reg64() or create a new function  both of them doesn't look good better to have this way only. - Krishna Chaitanya. > int mhi_read_reg64(...) { > u32 val_hi, val_lo; > u64 val; > > if (mhi_cntrl->read_reg64) { > ... > } else { > ... > val = FIELD_PREP(GENMASK(63, 32), val_hi)) | > FIELD_PREP(GENMASK(31, 0), val_lo)); > } > > return val > } > > > Konrad