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[79.50.55.97]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45055e2d3d0sm20037129f8f.34.2026.05.07.06.27.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 May 2026 06:28:00 -0700 (PDT) Message-ID: <6cc62409-9ca5-4db1-9526-65dd8b88981c@gmail.com> Date: Thu, 7 May 2026 15:27:58 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] iommu: arm-smmu-qcom: Ensure smmu is powered up in set_ttbr0_cfg To: Xilin Wu , Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260325-qcom_smmu_pmfix-v2-1-ba769a6ad0be@gmail.com> <330D3C56EBC6D08F+3d956321-39de-4308-a977-ad8f7101ed92@radxa.com> Content-Language: en-US From: Anna Maniscalco In-Reply-To: <330D3C56EBC6D08F+3d956321-39de-4308-a977-ad8f7101ed92@radxa.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 5/7/26 10:21 AM, Xilin Wu wrote: > On 3/26/2026 5:11 AM, Anna Maniscalco wrote: >> Previously the device was being accessed while potentially in a >> suspended state. >> >> Signed-off-by: Anna Maniscalco >> --- >> Changes in v2: >> - Simplify patch by acquiring device just around the call that needs it >> - Link to v1: >> https://lore.kernel.org/r/20260210-qcom_smmu_pmfix-v1-1-78b7143ac053@gmail.com >> --- >>   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 9 +++++++++ >>   1 file changed, 9 insertions(+) >> >> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> index 573085349df3..cab7d110aaf5 100644 >> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> @@ -231,6 +231,7 @@ static int qcom_adreno_smmu_set_ttbr0_cfg(const >> void *cookie, >>       struct io_pgtable *pgtable = >> io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); >>       struct arm_smmu_cfg *cfg = &smmu_domain->cfg; >>       struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; >> +    int ret; >>         /* The domain must have split pagetables already enabled */ >>       if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) >> @@ -260,8 +261,16 @@ static int qcom_adreno_smmu_set_ttbr0_cfg(const >> void *cookie, >>           cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); >>       } >>   +    ret = pm_runtime_resume_and_get(smmu_domain->smmu->dev); >> +    if (ret < 0) { >> +        dev_err(smmu_domain->smmu->dev, "failed to get runtime PM: >> %d\n", ret); >> +        return -ENODEV; >> +    } >> + >>       arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); >>   +    pm_runtime_put_autosuspend(smmu_domain->smmu->dev); >> + >>       return 0; >>   } >> >> --- >> base-commit: 50c4a49f7292b33b454ea1a16c4f77d6965405dc >> change-id: 20260210-qcom_smmu_pmfix-2aead2ba4e20 >> >> Best regards, > > May I ask what is the status of this patch? Without this patch, I can > trigger a crash easily on sc8280xp by running fastfetch multiple times. It's ready on my side so if someone could review I think it could be merged. > > Tested-by: Xilin Wu # sc8280xp-radxa-dragon-q8b > Best regards, -- Anna Maniscalco