[PATCH v3 26/27] soc: qcom: ubwc: sort out the rest of the UBWC swizzle settings

Dmitry Baryshkov
2026-03-12T13:30:18Z

Sort out the remaining UBWC swizzle values, using flags to control
whether level 2 and level 3 swizzling are enabled or not.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/soc/qcom/ubwc_config.c | 14 +++-----------
include/linux/soc/qcom/ubwc.h | 26 +++++++++++++-------------
2 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
index 49edfabb5e18..ccee20913115 100644
--- a/drivers/soc/qcom/ubwc_config.c
+++ b/drivers/soc/qcom/ubwc_config.c
@@ -18,8 +18,6 @@ static const struct qcom_ubwc_cfg_data no_ubwc_data = {

static const struct qcom_ubwc_cfg_data kaanapali_data = {
.ubwc_enc_version = UBWC_6_0,
- .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
- UBWC_SWIZZLE_ENABLE_LVL3,
.highest_bank_bit = 16,
};

@@ -40,7 +38,7 @@ static const struct qcom_ubwc_cfg_data qcm2290_data = {

static const struct qcom_ubwc_cfg_data sa8775p_data = {
.ubwc_enc_version = UBWC_4_0,
- .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3,
+ .flags = UBWC_FLAG_DISABLE_SWIZZLE_LVL2,
.highest_bank_bit = 13,
};

@@ -111,38 +109,32 @@ static const struct qcom_ubwc_cfg_data sm8150_data = {

static const struct qcom_ubwc_cfg_data sm8250_data = {
.ubwc_enc_version = UBWC_4_0,
- .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
- UBWC_SWIZZLE_ENABLE_LVL3,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
};

static const struct qcom_ubwc_cfg_data sm8350_data = {
.ubwc_enc_version = UBWC_4_0,
- .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
- UBWC_SWIZZLE_ENABLE_LVL3,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
};

static const struct qcom_ubwc_cfg_data sm8550_data = {
.ubwc_enc_version = UBWC_4_0,
- .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
- UBWC_SWIZZLE_ENABLE_LVL3,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
};

static const struct qcom_ubwc_cfg_data sm8750_data = {
.ubwc_enc_version = UBWC_5_0,
- .ubwc_swizzle = 6,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
};

static const struct qcom_ubwc_cfg_data glymur_data = {
.ubwc_enc_version = UBWC_5_0,
- .ubwc_swizzle = 0,
+ .flags = UBWC_FLAG_DISABLE_SWIZZLE_LVL2 |
+ UBWC_FLAG_DISABLE_SWIZZLE_LVL3,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
};
diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h
index 7c9506741001..a7372d9c25fb 100644
--- a/include/linux/soc/qcom/ubwc.h
+++ b/include/linux/soc/qcom/ubwc.h
@@ -14,15 +14,6 @@
struct qcom_ubwc_cfg_data {
u32 ubwc_enc_version;

- /**
- * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling.
- *
- * UBWC 1.0 always enables all three levels.
- * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
- * UBWC 4.0 adds the optional ability to disable levels 2 & 3.
- */
- u32 ubwc_swizzle;
-
/**
* @highest_bank_bit: Highest Bank Bit
*
@@ -30,6 +21,10 @@ struct qcom_ubwc_cfg_data {
* DDR bank. This should ideally use DRAM type detection.
*/
int highest_bank_bit;
+
+ unsigned int flags;
+#define UBWC_FLAG_DISABLE_SWIZZLE_LVL2 BIT(0)
+#define UBWC_FLAG_DISABLE_SWIZZLE_LVL3 BIT(1)
};

#define UBWC_1_0 0x10000000
@@ -98,11 +93,16 @@ static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg)
UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3;

- if (cfg->ubwc_enc_version < UBWC_4_0)
- return UBWC_SWIZZLE_ENABLE_LVL2 |
- UBWC_SWIZZLE_ENABLE_LVL3;
+ u32 ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
+ UBWC_SWIZZLE_ENABLE_LVL3;
+
+ if (cfg->flags & UBWC_FLAG_DISABLE_SWIZZLE_LVL2)
+ ubwc_swizzle &= ~UBWC_SWIZZLE_ENABLE_LVL2;
+
+ if (cfg->flags & UBWC_FLAG_DISABLE_SWIZZLE_LVL3)
+ ubwc_swizzle &= ~UBWC_SWIZZLE_ENABLE_LVL3;

- return cfg->ubwc_swizzle;
+ return ubwc_swizzle;
}

static inline u32 qcom_ubwc_version_tag(const struct qcom_ubwc_cfg_data *cfg)

--
2.47.3