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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d4c516dsm325677666b.154.2025.05.17.11.28.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 17 May 2025 11:28:52 -0700 (PDT) Message-ID: <6fa4959c-d733-4d50-904f-caf933e02da9@oss.qualcomm.com> Date: Sat, 17 May 2025 20:28:49 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 06/10] phy: qcom: Add M31 based eUSB2 PHY driver To: Wesley Cheng , Vinod Koul Cc: Melody Olvera , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20250409-sm8750_usb_master-v4-0-6ec621c98be6@oss.qualcomm.com> <20250409-sm8750_usb_master-v4-6-6ec621c98be6@oss.qualcomm.com> <0517c37d-b1ba-466e-bffd-9f47b0d458d5@quicinc.com> <5183b76b-8043-4309-b25d-e1ae505f929e@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <5183b76b-8043-4309-b25d-e1ae505f929e@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: i9Czy7MVW8AaxERf7jjvL2tCe6SWaCl8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE3MDE4MyBTYWx0ZWRfX9Z+dLpcJXx7B if9s/qN9rAjlag5X+KST0hMwgsLelki8U4vt573oArZJsMMGB1QvWMFZzqEX9Hl35tTA1A16S11 V/uAxdP9WGG5D7aQ+tE0PygIwNjk81yTr95OwvDINgu714BZjwJil1DSdBIAbhR+R0POg2CLwbK SFKu7np7pg0lkmnAVwOP7En3QALvfQC+fz5BR1o5aZpqKlE8aY79qhzT/DPEfvLw9ilgD2lDsj5 eq9zZPWELettCGo+Bnm9bAbh8IP2ZWKjHCqn0aqYL0PTqJUlUOYgUUGwtGc/hqEcZV2Ht6DM2/B 4Xny1e8Pa7S9rBvePAM0IZF0UhkhTx4xAwBvFn+z+53ne/W2m6+M5o+EE/lzYVCH4fw3brqHG33 LZLmNRqLeGZ6Q45RKsqgY4+0vW4cItSk8i6G7+exHkzEXX3xr6qAowQftVHyWHgxVa3NPQet X-Authority-Analysis: v=2.4 cv=H8Pbw/Yi c=1 sm=1 tr=0 ts=6828d569 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=jJrOw3FHAAAA:8 a=VwQbUJbxAAAA:8 a=7CQSdrXTAAAA:8 a=VM-KvOk4zruIL__GPFMA:9 a=QEXdDO2ut3YA:10 a=-FEs8UIgK8oA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-ORIG-GUID: i9Czy7MVW8AaxERf7jjvL2tCe6SWaCl8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-17_08,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 phishscore=0 mlxscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 impostorscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505170183 On 5/14/25 8:24 PM, Wesley Cheng wrote: > Hi Vinod, > > On 5/14/2025 1:33 AM, Vinod Koul wrote: >> On 16-04-25, 15:45, Wesley Cheng wrote: >>> Hi Vinod, >>> >>> On 4/10/2025 4:53 AM, Vinod Koul wrote: >>>> On 09-04-25, 10:48, Melody Olvera wrote: >>>> >>>>> +static int m31eusb2_phy_write_readback(void __iomem *base, u32 offset, >>>>> + const u32 mask, u32 val) >>>>> +{ >>>>> + u32 write_val; >>>>> + u32 tmp; >>>>> + >>>>> + tmp = readl_relaxed(base + offset); >>>>> + tmp &= ~mask; >>>>> + write_val = tmp | val; >>>>> + >>>>> + writel_relaxed(write_val, base + offset); >>>>> + >>>>> + tmp = readl_relaxed(base + offset); >>>> >>>> Why are you using _relaxed version here? >>>> >>> >>> No particular reason. I think someone pointed this out previously, and I >>> was open to use the non-relaxed variants, but I assume using the relaxed vs >>> non-relaxed apis comes down to preference in this case. >> >> Nope you cant! There _needs_ to be a specific reasons! >> When you are doing read, modify, write, it is very important to know the >> right version to use... >> > > I mean, its a write readback, which ensures the bus transaction is complete > based on [1], hence why **in this situation** it is up to preference. > > Otherwise, w/o the readback then we'd need to ensure writes are made > depending on the required sequencing (in spots where the sequence is > strictly defined), and that can be enforced using barriers. If you feel > like using the non-relaxed variant is preferred let me know. I can replace > it and remove the readback. Readback is stronger on arm64, as otherwise the writes may be buffered and not observable at the other endpoint even though the instruction has been issued, even if a barrier has been issued Some resources: https://youtu.be/i6DayghhA8Q https://lore.kernel.org/linux-arm-msm/20240618153419.GC2354@willie-the-truck/ https://developer.arm.com/documentation/ddi0487/latest sec B2.6.9 There's been a real bug observed (pun not intended): Commit 2f8cf2c3f3e3 ("clk: qcom: reset: Ensure write completion on reset de/assertion") Konrad