Re: [PATCH 2/2] clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks

[Imran Shaik <quic_imrashai@quicinc.com>]

On 4/14/2025 2:30 PM, Taniya Das wrote:
> Update the force mem core bit for UFS ICE clock and UFS PHY AXI clock to
> force the core on signal to remain active during halt state of the clk.
> If force mem core bit of the clock is not set, the memories of the
> subsystem will not retain the logic across power states. This is
> required for the MCQ feature of UFS.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  drivers/clk/qcom/gcc-x1e80100.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>

Thanks,
Imran