From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28FA78F5C; Wed, 27 Nov 2024 07:15:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732691717; cv=none; b=Hgt0nZ0nzpHWkwMVueMynN+ONw2anCPZSuOk0yuRZlS05DymeP1Hew/HMeH6lVE0PosyOqCHwxxvuskHs4TCgCHS5pOsfQ3Tx2bN+HL8ZuS9KWX9ykOJOH6978YBT+D89Bg48DmSoBCiKA2Yz49XrB2NSE2SdPn4VOTXprqxI/Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732691717; c=relaxed/simple; bh=XZWQ9oZ2HZ5yV4Z16lWMIhYwZGdeiyPdxl0C9N9vkGA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Y0a1JeyXPMzwTR+puXRxSIAXH7zahAf40EBL/ai/Pjuvys7gK5DMPWYkMWdGlYqeaWTPNe6ys20h/Blu0yAKfXzMRa5Z+14i2V5PiLLW8OqxfHI26JLJbJgwN269J5fYcDFX8CtNzGYgKEQ/z9dMRKfOQpjmvGzPtZADuNoH+v8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FTT/hOEq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FTT/hOEq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E32B0C4CECC; Wed, 27 Nov 2024 07:15:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732691716; bh=XZWQ9oZ2HZ5yV4Z16lWMIhYwZGdeiyPdxl0C9N9vkGA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=FTT/hOEqOJTMxAF6cZD9+rwSEUxOsNmpBu+MGdcyLbHv1uLfGk6H63xWcXfgpyklP y9W7MSTcQjs7Re4LxJxkPz9lTtysN3p9m/lIzcfBRk4TaYhmwSO0F6n0Y/VefF01Qk g++onz1YITqdo6Fr9ysXmxS+LwtmAvcqShSlTkwf9aSqd4acNp8xBJZlvTkkOqLYE/ yMtfSZelFVvcH6id4CMVjGw25OWqsLDuBgrphR1plyY6bMCEkyukRYnfFJX3LSvTqt phm2PJk6LAzOdycM0ofx7HfcNGygEreY3fAocDHWWp63BX5hjQx/snpKBiBL1TjKMY KVk5oNAEIa6+g== Message-ID: <70abadbf-b796-4434-b2d8-0675c18eee07@kernel.org> Date: Wed, 27 Nov 2024 08:15:08 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] dt-bindings: display/msm: Document MDSS on QCS8300 To: Yongxing Mou , Ritesh Kumar , Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Bjorn Andersson , Konrad Dybcio Cc: Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241127-mdss_qcs8300-v1-0-29b2c3ee95b8@quicinc.com> <20241127-mdss_qcs8300-v1-1-29b2c3ee95b8@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 27/11/2024 08:05, Yongxing Mou wrote: > Document the MDSS hardware found on the Qualcomm QCS8300 platform. > > Signed-off-by: Yongxing Mou Will fail testing, so only limited review. > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + #include > + #include > + > + mdss: display-subsystem@ae00000 { > + compatible = "qcom,qcs8300-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "mdp0-mem", > + "mdp1-mem", > + "cpu-cfg"; > + > + power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; > + > + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; > + > + interrupts = ; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x1000 0x402>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + status = "disabled"; No, your code cannot be disabled. > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,qcs8300-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + dpu_intf0_out: endpoint { > + remote-endpoint = <&mdss_dp0_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + > + opp-575000000 { > + opp-hz = /bits/ 64 <575000000>; > + required-opps = <&rpmhpd_opp_turbo>; > + }; > + > + opp-650000000 { > + opp-hz = /bits/ 64 <650000000>; > + required-opps = <&rpmhpd_opp_turbo_l1>; > + }; > + }; > + }; > + > + mdss_dp0: displayport-controller@af54000 { > + compatible = "qcom,qcs8300-dp"; > + > + pinctrl-0 = <&dp_hot_plug_det>; > + pinctrl-names = "default"; > + > + reg = <0 0xaf54000 0 0x104>, > + <0 0xaf54200 0 0x0c0>, > + <0 0xaf55000 0 0x770>, > + <0 0xaf56000 0 0x09c>; > + > + interrupt-parent = <&mdss>; > + interrupts = <12>; > + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, Messed alignment in multiple places. > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; > + clock-names = "core_iface", > + "core_aux", > + "ctrl_link", > + "ctrl_link_iface", > + "stream_pixel"; > + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; > + phys = <&mdss_edp_phy>; > + phy-names = "dp"; > + operating-points-v2 = <&dp_opp_table>; > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + #sound-dai-cells = <0>; > + status = "disabled"; No, your code cannot be disabled. > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss_dp0_in: endpoint { > + remote-endpoint = <&dpu_intf0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + mdss_dp_out: endpoint { }; > + }; > + }; > + > + dp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + Drop stray blank lines. > + }; > +... > Best regards, Krzysztof