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([2a00:f41:c97:23a9:35bc:df2e:d894:2c76]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b21dsm988109e87.173.2024.05.28.05.59.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 May 2024 05:59:55 -0700 (PDT) Message-ID: <7140cdb8-eda4-4dcd-b5e3-c4acdd01befb@linaro.org> Date: Tue, 28 May 2024 14:59:51 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings To: Bibek Kumar Patro , Rob Clark Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, dmitry.baryshkov@linaro.org, jsnitsel@redhat.com, quic_bjorande@quicinc.com, mani@kernel.org, quic_eberman@quicinc.com, robdclark@chromium.org, u.kleine-koenig@pengutronix.de, robh@kernel.org, vladimir.oltean@nxp.com, quic_pkondeti@quicinc.com, quic_molvera@quicinc.com, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org References: <20240123144543.9405-1-quic_bibekkum@quicinc.com> <20240123144543.9405-4-quic_bibekkum@quicinc.com> <51b2bd40-888d-4ee4-956f-c5239c5be9e9@linaro.org> <0a867cd1-8d99-495e-ae7e-a097fc9c00e9@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <0a867cd1-8d99-495e-ae7e-a097fc9c00e9@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 5/15/24 15:59, Bibek Kumar Patro wrote: > > > On 5/10/2024 6:32 PM, Konrad Dybcio wrote: >> On 10.05.2024 2:52 PM, Bibek Kumar Patro wrote: >>> >>> >>> On 5/1/2024 12:30 AM, Rob Clark wrote: >>>> On Tue, Jan 23, 2024 at 7:00 AM Bibek Kumar Patro >>>> wrote: >>>>> >>>>> Currently in Qualcomm  SoCs the default prefetch is set to 1 which allows >>>>> the TLB to fetch just the next page table. MMU-500 features ACTLR >>>>> register which is implementation defined and is used for Qualcomm SoCs >>>>> to have a custom prefetch setting enabling TLB to prefetch the next set >>>>> of page tables accordingly allowing for faster translations. >>>>> >>>>> ACTLR value is unique for each SMR (Stream matching register) and stored >>>>> in a pre-populated table. This value is set to the register during >>>>> context bank initialisation. >>>>> >>>>> Signed-off-by: Bibek Kumar Patro >>>>> --- >> >> [...] >> >>>>> + >>>>> +               for_each_cfg_sme(cfg, fwspec, j, idx) { >>>>> +                       smr = &smmu->smrs[idx]; >>>>> +                       if (smr_is_subset(smr, id, mask)) { >>>>> +                               arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR, >>>>> +                                               actlrcfg[i].actlr); >>>> >>>> So, this makes ACTLR look like kind of a FIFO.  But I'm looking at >>>> downstream kgsl's PRR thing (which we'll need to implement vulkan >>>> sparse residency), and it appears to be wanting to set BIT(5) in ACTLR >>>> to enable PRR. >>>> >>>>           val = KGSL_IOMMU_GET_CTX_REG(ctx, KGSL_IOMMU_CTX_ACTLR); >>>>           val |= FIELD_PREP(KGSL_IOMMU_ACTLR_PRR_ENABLE, 1); >>>>           KGSL_IOMMU_SET_CTX_REG(ctx, KGSL_IOMMU_CTX_ACTLR, val); >>>> >>>> Any idea how this works?  And does it need to be done before or after >>>> the ACTLR programming done in this patch? >>>> >>>> BR, >>>> -R >>>> >>> >>> Hi Rob, >>> >>> Can you please help provide some more clarification on the FIFO part? By FIFO are you referring to the storing of ACTLR data in the table? >>> >>> Thanks for pointing to the downstream implementation of kgsl driver for >>> the PRR bit. Since kgsl driver is already handling this PRR bit's >>> setting, this makes setting the PRR BIT(5) by SMMU driver redundant. >> >> The kgsl driver is not present upstream. >> > > Right kgsl is not present upstream, it would be better to avoid configuring the PRR bit and can be handled by kgsl directly in downstream. No! Upstream is not a dumping ground to reduce your technical debt. There is no kgsl driver upstream, so this ought to be handled here, in the iommu driver (as poking at hardware A from driver B is usually not good practice). > >>> Thanks for bringing up this point. >>> I will send v10 patch series removing this BIT(5) setting from the ACTLR >>> table. >> >> I think it's generally saner to configure the SMMU from the SMMU driver.. > > Yes, agree on this. But since PRR bit is not directly related to SMMU > configuration so I think it would be better to remove this PRR bit > setting from SMMU driver based on my understanding. Why is it not related? We still don't know what it does. Konrad