From: Lizhi Hou <lizhi.hou@amd.com>
To: Jeffrey Hugo <quic_jhugo@quicinc.com>, <quic_carlv@quicinc.com>,
<manivannan.sadhasivam@linaro.org>, <quic_yabdulra@quicinc.com>,
<quic_mattleun@quicinc.com>, <quic_thanson@quicinc.com>
Cc: <ogabbay@kernel.org>, <jacek.lawrynowicz@linux.intel.com>,
<linux-arm-msm@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>, <mhi@lists.linux.dev>
Subject: Re: [PATCH 5/7] accel/qaic: Mask out SR-IOV PCI resources
Date: Fri, 13 Dec 2024 16:20:07 -0800 [thread overview]
Message-ID: <730f1e2f-d69b-e142-62aa-3f9971129a8b@amd.com> (raw)
In-Reply-To: <20241213213340.2551697-6-quic_jhugo@quicinc.com>
On 12/13/24 13:33, Jeffrey Hugo wrote:
> From: Youssef Samir <quic_yabdulra@quicinc.com>
>
> During the initialization of the qaic device, pci_select_bars() is
> used to fetch a bitmask of the BARs exposed by the device. On devices
> that have Virtual Functions capabilities, the bitmask includes SR-IOV
> BARs.
>
> Use a mask to filter out SR-IOV BARs if they exist.
>
> Signed-off-by: Youssef Samir <quic_yabdulra@quicinc.com>
> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
> ---
> drivers/accel/qaic/qaic_drv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/accel/qaic/qaic_drv.c b/drivers/accel/qaic/qaic_drv.c
> index ce0428f6cb82..00fa07aebacd 100644
> --- a/drivers/accel/qaic/qaic_drv.c
> +++ b/drivers/accel/qaic/qaic_drv.c
> @@ -431,7 +431,7 @@ static int init_pci(struct qaic_device *qdev, struct pci_dev *pdev)
> int bars;
> int ret;
>
> - bars = pci_select_bars(pdev, IORESOURCE_MEM);
> + bars = pci_select_bars(pdev, IORESOURCE_MEM) & 0x3f;
>
> /* make sure the device has the expected BARs */
> if (bars != (BIT(0) | BIT(2) | BIT(4))) {
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
next prev parent reply other threads:[~2024-12-14 0:20 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-13 21:33 [PATCH 0/7] accel/qaic: Initial AIC200 support Jeffrey Hugo
2024-12-13 21:33 ` [PATCH 1/7] bus: mhi: host: Refactor BHI/BHIe based firmware loading Jeffrey Hugo
2025-01-07 11:06 ` Jacek Lawrynowicz
2025-01-08 5:24 ` Manivannan Sadhasivam
2025-01-17 16:21 ` Jeffrey Hugo
2024-12-13 21:33 ` [PATCH 2/7] bus: mhi: host: Add a policy to enable image transfer via BHIe in PBL Jeffrey Hugo
2025-01-07 11:12 ` Jacek Lawrynowicz
2025-01-08 5:42 ` Manivannan Sadhasivam
2025-01-17 16:45 ` Jeffrey Hugo
2024-12-13 21:33 ` [PATCH 3/7] accel/qaic: Allocate an exact number of MSIs Jeffrey Hugo
2024-12-13 23:43 ` Lizhi Hou
2024-12-13 21:33 ` [PATCH 4/7] accel/qaic: Add support for MSI-X Jeffrey Hugo
2024-12-13 23:49 ` Lizhi Hou
2024-12-13 21:33 ` [PATCH 5/7] accel/qaic: Mask out SR-IOV PCI resources Jeffrey Hugo
2024-12-14 0:20 ` Lizhi Hou [this message]
2024-12-13 21:33 ` [PATCH 6/7] accel/qaic: Add config structs for supported cards Jeffrey Hugo
2024-12-14 0:35 ` Lizhi Hou
2024-12-20 17:15 ` Jeffrey Hugo
2024-12-20 18:08 ` Lizhi Hou
2024-12-13 21:33 ` [PATCH 7/7] accel/qaic: Add AIC200 support Jeffrey Hugo
2024-12-14 0:49 ` Lizhi Hou
2024-12-20 17:26 ` Jeffrey Hugo
2024-12-20 17:33 ` Lizhi Hou
2024-12-20 17:50 ` Jeffrey Hugo
2024-12-20 18:07 ` Lizhi Hou
2024-12-28 0:19 ` kernel test robot
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