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Mon, 17 Mar 2025 02:07:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFb2/5Yz0QBAf85V3J3MJIKQQYTZZtL2r4Zp4gVmTlQYnG653reK868zYsRjio4CbC3TLgJeQ== X-Received: by 2002:a05:6a00:2e15:b0:736:5753:12f7 with SMTP id d2e1a72fcca58-7372236c48amr15633816b3a.3.1742202473230; Mon, 17 Mar 2025 02:07:53 -0700 (PDT) Received: from [10.92.192.202] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73711557ee8sm7351197b3a.52.2025.03.17.02.07.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Mar 2025 02:07:52 -0700 (PDT) Message-ID: <74ff7b72-94d6-cd19-06c4-09cddc885cb0@oss.qualcomm.com> Date: Mon, 17 Mar 2025 14:37:45 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v4 08/10] PCI: pwrctrl: Add power control driver for tc956x To: Konrad Dybcio , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski Cc: quic_vbadigan@quicnic.com, amitk@kernel.org, dmitry.baryshkov@linaro.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com, Bartosz Golaszewski References: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> <20250225-qps615_v4_1-v4-8-e08633a7bdf8@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: lTFlqOFpFLeHzNKa5qkkFwnBaNRKfssh X-Proofpoint-GUID: lTFlqOFpFLeHzNKa5qkkFwnBaNRKfssh X-Authority-Analysis: v=2.4 cv=R7kDGcRX c=1 sm=1 tr=0 ts=67d7e66a cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=LmMbr2wudRAhekVMzXwA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-17_03,2025-03-17_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 malwarescore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503170067 On 2/25/2025 5:39 PM, Konrad Dybcio wrote: > On 25.02.2025 10:34 AM, Krishna Chaitanya Chundru wrote: >> TC956x is a PCIe switch which has one upstream and three downstream >> ports. To one of the downstream ports ethernet MAC is connected as endpoint >> device. Other two downstream ports are supposed to connect to external >> device. One Host can connect to TC956x by upstream port. TC956x switch >> needs to be configured after powering on and before PCIe link was up. >> >> The PCIe controller driver already enables link training at the host side >> even before this driver probe happens, due to this when driver enables >> power to the switch it participates in the link training and PCIe link >> may come up before configuring the switch through i2c. Once the link is >> up the configuration done through i2c will not have any affect.To prevent >> the host from participating in link training, disable link training on the >> host side to ensure the link does not come up before the switch is >> configured via I2C. >> >> Based up on dt property and type of the port, tc956x is configured >> through i2c. >> >> Signed-off-by: Krishna Chaitanya Chundru >> Reviewed-by: Bjorn Andersson >> Reviewed-by: Bartosz Golaszewski >> --- > > >> +struct tc956x_pwrctrl_cfg { >> + u32 l0s_delay; >> + u32 l1_delay; >> + u32 tx_amp; >> + u8 nfts[2]; /* GEN1 & GEN2*/ > > GEN2 */ > > [...] > >> +static int tc956x_pwrctrl_set_l0s_l1_entry_delay(struct tc956x_pwrctrl_ctx *ctx, >> + enum tc956x_pwrctrl_ports port, bool is_l1, u32 ns) >> +{ >> + u32 rd_val, units; >> + int ret; >> + >> + if (!ns) >> + return 0; >> + >> + /* convert to units of 256ns */ >> + units = ns / 256; > > Should we round up here, so that values in 1 <= x < 256 give a delay > value of 1 unit? Or maybe such values are never expected? > I will add a check above to return if ns < 256 as 0 is not expected value. > [...] > >> +static int tc956x_pwrctrl_set_tx_amplitude(struct tc956x_pwrctrl_ctx *ctx, >> + enum tc956x_pwrctrl_ports port, u32 amp) >> +{ >> + int port_access; >> + >> + if (amp < TC956X_TX_MARGIN_MIN_VAL) >> + return 0; >> + >> + /* txmargin = (Amp(uV) - 400000) / 3125 */ > > double space > >> + amp = (amp - TC956X_TX_MARGIN_MIN_VAL) / 3125; > > similarly here, is 0 an expected value for 1 <= x < 3125? > Here 0 is expected value in this case. - Krishna Chaitanya. > Konrad