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Wed, 27 Nov 2024 07:00:46 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AR70kuY026035 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 27 Nov 2024 07:00:46 GMT Received: from [10.253.38.8] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 26 Nov 2024 23:00:42 -0800 Message-ID: <75fb42cc-1cc5-4dd3-924c-e6fda4061f03@quicinc.com> Date: Wed, 27 Nov 2024 15:00:38 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: qcs615-ride: Enable ethernet node From: Yijie Yang To: Andrew Lunn , Konrad Dybcio CC: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , , , , References: <20241118-dts_qcs615-v2-0-e62b924a3cbd@quicinc.com> <20241118-dts_qcs615-v2-2-e62b924a3cbd@quicinc.com> <89a4f120-6cfd-416d-ab55-f0bdf069d9ce@quicinc.com> <3c69423e-ba80-487f-b585-1e4ffb4137b6@lunn.ch> <2556b02c-f884-40c2-a0d4-0c87da6e5332@quicinc.com> Content-Language: en-US In-Reply-To: <2556b02c-f884-40c2-a0d4-0c87da6e5332@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _Sw2n69pV_5KQZultUUqlaXlxy3wsuoo X-Proofpoint-ORIG-GUID: _Sw2n69pV_5KQZultUUqlaXlxy3wsuoo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 adultscore=0 spamscore=0 impostorscore=0 priorityscore=1501 phishscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411270056 On 2024-11-27 14:17, Yijie Yang wrote: > > > On 2024-11-22 21:19, Andrew Lunn wrote: >>>>>>    +ðernet { >>>>>> +    status = "okay"; >>>>>> + >>>>>> +    pinctrl-0 = <ðernet_defaults>; >>>>>> +    pinctrl-names = "default"; >>>>>> + >>>>>> +    phy-handle = <&rgmii_phy>; >>>>>> +    phy-mode = "rgmii"; >>>>> >>>>> That is unusual. Does the board have extra long clock lines? >>>> >>>> Do you mean to imply that using RGMII mode is unusual? While the >>>> EMAC controller supports various modes, due to hardware design >>>> limitations, only RGMII mode can be effectively implemented. >>> >>> Is that a board-specific issue, or something that concerns the SoC >>> itself? >> >> Lots of developers gets this wrong.... Searching the mainline list for >> patchs getting it wrong and the explanation i have given in the past >> might help. >> >> The usual setting here is 'rgmmii-id', which means something needs to >> insert a 2ns delay on the clock lines. This is not always true, a very >> small number of boards use extra long clock likes on the PCB to add >> the needed 2ns delay. >> >> Now, if 'rgmii' does work, it means something else is broken >> somewhere. I will let you find out what. > > The 'rgmii' does function correctly, but it does not necessarily mean > that a time delay is required at the board level. The EPHY can also > compensate for the time skew. I was mistaken earlier; it is actually the EMAC that will introduce a time skew by shifting the phase of the clock in 'rgmii' mode. > >> >>>>>> +    max-speed = <1000>; >>>>> >>>>> Why do you have this property? It is normally used to slow the MAC >>>>> down because of issues at higher speeds. >>>> >>>> According to the databoot, the EMAC in RGMII mode can support speeds >>>> of up to 1Gbps. >>> >>> I believe the question Andrew is asking is "how is that effectively >>> different from the default setting (omitting the property)?" >> >> Correct. If there are no issues at higher speeds, you don't need >> this. phylib will ask the PHY what it is capable of, and limit the >> negotiated speeds to its capabilities. Occasionally you do see an >> RGMII PHY connected to a MII MAC, because a RGMII PHY is cheaper... >> >>     Andrew > > It does unnecessary, I will remove it. > -- Best Regards, Yijie