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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: Mmpk4rsDTjciuHJQEEGbDdMYGJqu692K X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAzMSBTYWx0ZWRfX3Aceyn+8rfj3 vyVXxtooHgY8HD31brSS5svSfqpbUykntOWDDRmtsEIZdGHupEpTnHThUDmAjUUGD7q5/PS5KN7 gtU/z0+SZFyizD5L2Tj4iOo97YY2q2JF0XB2wncTckOkdGxBosXnuQiuyUrkwHKx0xSmcNsUWli bOHBhLTf60wWhsTqMdzAW17UqWCbyUUQS4MrNx1Hc6E0NbCNKLhjwXyIEDqA81zg20W39wX1OwU 8vCabOPklhXGT66FEXVzo4SHRPxK8HSo/cLGNTd4sE3FSzsaHYeia4307Njca8E/ZhteXUqL0fQ /s7zUmv5XryKP812q2VRoM28vwPZdDXJjsJ9ZI0ebxk+vdzsXgyIEt25zm4t1vmiMDjVw6HsWip P32wveHPWs4bitwTSh8n2TJVXIHGEQ== X-Authority-Analysis: v=2.4 cv=QYNrf8bv c=1 sm=1 tr=0 ts=68f79b17 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=PLUc99ambSscJNFV4OcA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: Mmpk4rsDTjciuHJQEEGbDdMYGJqu692K X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-21_02,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 malwarescore=0 clxscore=1015 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180031 On 10/19/2025 2:40 PM, Krzysztof Kozlowski wrote: > On 17/10/2025 19:08, Akhil P Oommen wrote: >> A612 GPU has a new IP called RGMU (Reduced Graphics Management Unit) >> which replaces GMU. But it doesn't do clock or voltage scaling. So we >> need the gpu core clock in the GPU node along with the power domain to >> do clock and voltage scaling from the kernel. Update the bindings to >> describe this GPU. >> >> Signed-off-by: Akhil P Oommen >> --- >> .../devicetree/bindings/display/msm/gpu.yaml | 31 ++++++++++++++++++++-- >> 1 file changed, 29 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml >> index 3696b083e353031a496a1f299d8f373270ca562d..efc529e82bc198e7c3c89a5eecb6f929960a8de9 100644 >> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml >> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml >> @@ -45,11 +45,11 @@ properties: >> - const: amd,imageon >> >> clocks: >> - minItems: 2 >> + minItems: 1 >> maxItems: 7 >> >> clock-names: >> - minItems: 2 >> + minItems: 1 >> maxItems: 7 >> >> reg: >> @@ -388,6 +388,33 @@ allOf: >> required: >> - clocks >> - clock-names >> + >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: qcom,adreno-612.0 >> + then: >> + properties: >> + clocks: >> + minItems: 1 > > Drop, it's implied. > > >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: core >> + description: GPU Core clock >> + > > Missing constraint for 'reg'. I suppose we should add reg property with a list of (items:) reg descriptions. No need for 'min/minxItems constraints as it is not flexible. > >> + reg-names: >> + minItems: 1 > > Drop. MMIO range is not flexible. Ack. -Akhil > >> + items: >> + - const: kgsl_3d0_reg_memory >> + - const: cx_dbgc >> + > Best regards, > Krzysztof