[PATCH RFC v2 0/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[PATCH RFC v2 0/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Krzysztof Kozlowski]

Hi,

Changes in v2:
- Patch #1: Add RPMHPD_MXC (Konrad)
- Link to v1: https://lore.kernel.org/r/20250714-b4-sm8750-iris-dts-v1-0-93629b246d2e@linaro.org

RFC because depends on old series (6 months old!) which received
feedback and nothing happened since that time.  I assume author
abandoned that series, but unfortunately unmerged bindings for
qcom,sm8750-videocc block this patchset:
https://lore.kernel.org/all/20241206-sm8750_videocc-v1-0-5da6e7eea2bd@quicinc.com/

The bindings for new compatible qcom,sm8750-iris:
https://lore.kernel.org/r/20250804-sm8750-iris-v2-0-6d78407f8078@linaro.org

Best regards,
Krzysztof

---
Krzysztof Kozlowski (3):
      arm64: dts: qcom: sm8750: Add Iris VPU v3.5
      [DO NOT MERGE] arm64: dts: qcom: sm8750-mtp: Enable Iris codec
      [DO NOT MERGE] arm64: dts: qcom: sm8750-qrd: Enable Iris codec

 arch/arm64/boot/dts/qcom/sm8750-mtp.dts |   4 ++
 arch/arm64/boot/dts/qcom/sm8750-qrd.dts |   4 ++
 arch/arm64/boot/dts/qcom/sm8750.dtsi    | 113 ++++++++++++++++++++++++++++++++
 3 files changed, 121 insertions(+)
---
base-commit: 709a73d51f11d75ee2aee4f690e4ecd8bc8e9bf3
change-id: 20250714-b4-sm8750-iris-dts-ebdb5dc4ee27
prerequisite-message-id: 20241206-sm8750_videocc-v1-0-5da6e7eea2bd@quicinc.com
prerequisite-patch-id: ada17af875101625f7754335fabc909c8ab9cd20
prerequisite-patch-id: 3cb47a7c47cd96e02b5a4a05490088541f97c629
prerequisite-patch-id: 8c77b8e0c611b5e28086a456157940d773b323ab

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

[PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Krzysztof Kozlowski]

Add Iris video codec to SM8750 SoC, which comes with significantly
different powering up sequence than previous SM8650, thus different
clocks and resets.  For consistency keep existing clock and clock-names
naming, so the list shares common part.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

---

qcom,sm8750-videocc bindings and clock headers dependency (will fail
build):
https://lore.kernel.org/all/20241206-sm8750_videocc-v1-0-5da6e7eea2bd@quicinc.com/

qcom,sm8750-iris bindings:
https://lore.kernel.org/r/20250804-sm8750-iris-v2-0-6d78407f8078@linaro.org
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 113 +++++++++++++++++++++++++++++++++++
 1 file changed, 113 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 4643705021c6ca095a16d8d7cc3adac920b21e82..cea4df8b4673c938428ce1b6f3f5cc9e5be3d3ea 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sm8750-gcc.h>
 #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
+#include <dt-bindings/clock/qcom,sm8750-videocc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
@@ -2581,6 +2582,118 @@ data-pins {
 			};
 		};
 
+		iris: video-codec@aa00000 {
+			compatible = "qcom,sm8750-iris";
+			reg = <0x0 0x0aa00000 0x0 0xf0000>;
+
+			clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+				 <&videocc VIDEO_CC_MVS0C_CLK>,
+				 <&videocc VIDEO_CC_MVS0_CLK>,
+				 <&gcc GCC_VIDEO_AXI1_CLK>,
+				 <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
+				 <&videocc VIDEO_CC_MVS0_FREERUN_CLK>;
+			clock-names = "iface",
+				      "core",
+				      "vcodec0_core",
+				      "iface1",
+				      "core_freerun",
+				      "vcodec0_core_freerun";
+
+			dma-coherent;
+			iommus = <&apps_smmu 0x1940 0>,
+				 <&apps_smmu 0x1947 0>;
+
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+					<&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "cpu-cfg",
+					     "video-mem";
+
+			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+			memory-region = <&video_mem>;
+
+			operating-points-v2 = <&iris_opp_table>;
+
+			power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+					<&videocc VIDEO_CC_MVS0_GDSC>,
+					<&rpmhpd RPMHPD_MXC>,
+					<&rpmhpd RPMHPD_MMCX>;
+			power-domain-names = "venus",
+					     "vcodec0",
+					     "mxc",
+					     "mmcx";
+
+			resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+				 <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
+				 <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
+				 <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>;
+			reset-names = "bus0",
+				      "bus1",
+				      "core",
+				      "vcodec0_core";
+
+			/*
+			 * IRIS firmware is signed by vendors, only
+			 * enable in boards where the proper signed firmware
+			 * is available.
+			 */
+			status = "disabled";
+
+			iris_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-240000000 {
+					opp-hz = /bits/ 64 <240000000>;
+					required-opps = <&rpmhpd_opp_low_svs_d1>,
+							<&rpmhpd_opp_low_svs_d1>;
+				};
+
+				opp-338000000 {
+					opp-hz = /bits/ 64 <338000000>;
+					required-opps = <&rpmhpd_opp_low_svs>,
+							<&rpmhpd_opp_low_svs>;
+				};
+
+				opp-420000000 {
+					opp-hz = /bits/ 64 <420000000>;
+					required-opps = <&rpmhpd_opp_svs>,
+							<&rpmhpd_opp_svs>;
+				};
+
+				opp-444000000 {
+					opp-hz = /bits/ 64 <444000000>;
+					required-opps = <&rpmhpd_opp_svs_l1>,
+							<&rpmhpd_opp_svs_l1>;
+				};
+
+				opp-533333334 {
+					opp-hz = /bits/ 64 <533333334>;
+					required-opps = <&rpmhpd_opp_nom>,
+							<&rpmhpd_opp_nom>;
+				};
+
+				opp-630000000 {
+					opp-hz = /bits/ 64 <630000000>;
+					required-opps = <&rpmhpd_opp_turbo>,
+							<&rpmhpd_opp_turbo>;
+				};
+			};
+		};
+
+		videocc: clock-controller@aaf0000 {
+			compatible = "qcom,sm8750-videocc";
+			reg = <0x0 0x0aaf0000 0x0 0x10000>;
+			clocks = <&bi_tcxo_div2>,
+				 <&gcc GCC_VIDEO_AHB_CLK>;
+			power-domains = <&rpmhpd RPMHPD_MMCX>,
+					<&rpmhpd RPMHPD_MXC>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,sm8750-pdc", "qcom,pdc";
 			reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;

-- 
2.48.1

Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Konrad Dybcio]

On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
> Add Iris video codec to SM8750 SoC, which comes with significantly
> different powering up sequence than previous SM8650, thus different
> clocks and resets.  For consistency keep existing clock and clock-names
> naming, so the list shares common part.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> ---

[...]

> +			iris_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-240000000 {
> +					opp-hz = /bits/ 64 <240000000>;
> +					required-opps = <&rpmhpd_opp_low_svs_d1>,
> +							<&rpmhpd_opp_low_svs_d1>;
> +				};
> +
> +				opp-338000000 {
> +					opp-hz = /bits/ 64 <338000000>;
> +					required-opps = <&rpmhpd_opp_low_svs>,
> +							<&rpmhpd_opp_low_svs>;
> +				};
> +
> +				opp-420000000 {
> +					opp-hz = /bits/ 64 <420000000>;
> +					required-opps = <&rpmhpd_opp_svs>,
> +							<&rpmhpd_opp_svs>;
> +				};
> +
> +				opp-444000000 {
> +					opp-hz = /bits/ 64 <444000000>;
> +					required-opps = <&rpmhpd_opp_svs_l1>,
> +							<&rpmhpd_opp_svs_l1>;
> +				};
> +
> +				opp-533333334 {
> +					opp-hz = /bits/ 64 <533333334>;
> +					required-opps = <&rpmhpd_opp_nom>,
> +							<&rpmhpd_opp_nom>;
> +				};

There's an additional OPP: 570 MHz @ NOM_L1

+Dmitry, Vikash, please make sure you're OK with the iommu entries

the other properties look OK

Konrad

Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Krzysztof Kozlowski]

On 12/08/2025 16:21, Konrad Dybcio wrote:
> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
>> Add Iris video codec to SM8750 SoC, which comes with significantly
>> different powering up sequence than previous SM8650, thus different
>> clocks and resets.  For consistency keep existing clock and clock-names
>> naming, so the list shares common part.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>
>> ---
> 
> [...]
> 
>> +			iris_opp_table: opp-table {
>> +				compatible = "operating-points-v2";
>> +
>> +				opp-240000000 {
>> +					opp-hz = /bits/ 64 <240000000>;
>> +					required-opps = <&rpmhpd_opp_low_svs_d1>,
>> +							<&rpmhpd_opp_low_svs_d1>;
>> +				};
>> +
>> +				opp-338000000 {
>> +					opp-hz = /bits/ 64 <338000000>;
>> +					required-opps = <&rpmhpd_opp_low_svs>,
>> +							<&rpmhpd_opp_low_svs>;
>> +				};
>> +
>> +				opp-420000000 {
>> +					opp-hz = /bits/ 64 <420000000>;
>> +					required-opps = <&rpmhpd_opp_svs>,
>> +							<&rpmhpd_opp_svs>;
>> +				};
>> +
>> +				opp-444000000 {
>> +					opp-hz = /bits/ 64 <444000000>;
>> +					required-opps = <&rpmhpd_opp_svs_l1>,
>> +							<&rpmhpd_opp_svs_l1>;
>> +				};
>> +
>> +				opp-533333334 {
>> +					opp-hz = /bits/ 64 <533333334>;
>> +					required-opps = <&rpmhpd_opp_nom>,
>> +							<&rpmhpd_opp_nom>;
>> +				};
> 
> There's an additional OPP: 570 MHz @ NOM_L1
> 
> +Dmitry, Vikash, please make sure you're OK with the iommu entries


That opp has troubles with clock, so would need some fixed in videocc or
iris, AFAIK. Otherwise you will just PM OPP failures. I can add it
though, at the end  DTS should be independent of drivers. :)

Best regards,
Krzysztof

Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Konrad Dybcio]

On 8/12/25 4:24 PM, Krzysztof Kozlowski wrote:
> On 12/08/2025 16:21, Konrad Dybcio wrote:
>> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
>>> Add Iris video codec to SM8750 SoC, which comes with significantly
>>> different powering up sequence than previous SM8650, thus different
>>> clocks and resets.  For consistency keep existing clock and clock-names
>>> naming, so the list shares common part.
>>>
>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>
>>> ---
>>
>> [...]
>>
>>> +			iris_opp_table: opp-table {
>>> +				compatible = "operating-points-v2";
>>> +
>>> +				opp-240000000 {
>>> +					opp-hz = /bits/ 64 <240000000>;
>>> +					required-opps = <&rpmhpd_opp_low_svs_d1>,
>>> +							<&rpmhpd_opp_low_svs_d1>;
>>> +				};
>>> +
>>> +				opp-338000000 {
>>> +					opp-hz = /bits/ 64 <338000000>;
>>> +					required-opps = <&rpmhpd_opp_low_svs>,
>>> +							<&rpmhpd_opp_low_svs>;
>>> +				};
>>> +
>>> +				opp-420000000 {
>>> +					opp-hz = /bits/ 64 <420000000>;
>>> +					required-opps = <&rpmhpd_opp_svs>,
>>> +							<&rpmhpd_opp_svs>;
>>> +				};
>>> +
>>> +				opp-444000000 {
>>> +					opp-hz = /bits/ 64 <444000000>;
>>> +					required-opps = <&rpmhpd_opp_svs_l1>,
>>> +							<&rpmhpd_opp_svs_l1>;
>>> +				};
>>> +
>>> +				opp-533333334 {
>>> +					opp-hz = /bits/ 64 <533333334>;
>>> +					required-opps = <&rpmhpd_opp_nom>,
>>> +							<&rpmhpd_opp_nom>;
>>> +				};
>>
>> There's an additional OPP: 570 MHz @ NOM_L1
>>
>> +Dmitry, Vikash, please make sure you're OK with the iommu entries
> 
> 
> That opp has troubles with clock, so would need some fixed in videocc or
> iris, AFAIK. Otherwise you will just PM OPP failures. I can add it
> though, at the end  DTS should be independent of drivers. :)

Weird, there's an entry in the frequency table for it (well, * 3 the
rate) and it comes out of the same PLL as other ones.. what sort of
opp failures do you see?

Konrad

Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Krzysztof Kozlowski]

On 12/08/2025 16:26, Konrad Dybcio wrote:
> On 8/12/25 4:24 PM, Krzysztof Kozlowski wrote:
>> On 12/08/2025 16:21, Konrad Dybcio wrote:
>>> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
>>>> Add Iris video codec to SM8750 SoC, which comes with significantly
>>>> different powering up sequence than previous SM8650, thus different
>>>> clocks and resets.  For consistency keep existing clock and clock-names
>>>> naming, so the list shares common part.
>>>>
>>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>>
>>>> ---
>>>
>>> [...]
>>>
>>>> +			iris_opp_table: opp-table {
>>>> +				compatible = "operating-points-v2";
>>>> +
>>>> +				opp-240000000 {
>>>> +					opp-hz = /bits/ 64 <240000000>;
>>>> +					required-opps = <&rpmhpd_opp_low_svs_d1>,
>>>> +							<&rpmhpd_opp_low_svs_d1>;
>>>> +				};
>>>> +
>>>> +				opp-338000000 {
>>>> +					opp-hz = /bits/ 64 <338000000>;
>>>> +					required-opps = <&rpmhpd_opp_low_svs>,
>>>> +							<&rpmhpd_opp_low_svs>;
>>>> +				};
>>>> +
>>>> +				opp-420000000 {
>>>> +					opp-hz = /bits/ 64 <420000000>;
>>>> +					required-opps = <&rpmhpd_opp_svs>,
>>>> +							<&rpmhpd_opp_svs>;
>>>> +				};
>>>> +
>>>> +				opp-444000000 {
>>>> +					opp-hz = /bits/ 64 <444000000>;
>>>> +					required-opps = <&rpmhpd_opp_svs_l1>,
>>>> +							<&rpmhpd_opp_svs_l1>;
>>>> +				};
>>>> +
>>>> +				opp-533333334 {
>>>> +					opp-hz = /bits/ 64 <533333334>;
>>>> +					required-opps = <&rpmhpd_opp_nom>,
>>>> +							<&rpmhpd_opp_nom>;
>>>> +				};
>>>
>>> There's an additional OPP: 570 MHz @ NOM_L1
>>>
>>> +Dmitry, Vikash, please make sure you're OK with the iommu entries
>>
>>
>> That opp has troubles with clock, so would need some fixed in videocc or
>> iris, AFAIK. Otherwise you will just PM OPP failures. I can add it
>> though, at the end  DTS should be independent of drivers. :)
> 
> Weird, there's an entry in the frequency table for it (well, * 3 the
> rate) and it comes out of the same PLL as other ones.. what sort of

You mean freq_tbl in P_VIDEO_CC_PLL0_OUT_MAIN? Yeah, I also saw that.

> opp failures do you see?

Only:

[    9.306006] qcom-iris aa00000.video-codec: dev_pm_opp_set_rate:
failed to find OPP for freq 630000000 (-34)
[    9.316078] qcom-iris aa00000.video-codec: power on failed
[    9.322001] qcom-iris aa00000.video-codec: core init failed


Best regards,
Krzysztof

Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Krzysztof Kozlowski]

On 12/08/2025 16:39, Krzysztof Kozlowski wrote:
>>>>> +
>>>>> +				opp-533333334 {
>>>>> +					opp-hz = /bits/ 64 <533333334>;
>>>>> +					required-opps = <&rpmhpd_opp_nom>,
>>>>> +							<&rpmhpd_opp_nom>;
>>>>> +				};
>>>>
>>>> There's an additional OPP: 570 MHz @ NOM_L1
>>>>
>>>> +Dmitry, Vikash, please make sure you're OK with the iommu entries
>>>
>>>
>>> That opp has troubles with clock, so would need some fixed in videocc or
>>> iris, AFAIK. Otherwise you will just PM OPP failures. I can add it
>>> though, at the end  DTS should be independent of drivers. :)
>>
>> Weird, there's an entry in the frequency table for it (well, * 3 the
>> rate) and it comes out of the same PLL as other ones.. what sort of
> 
> You mean freq_tbl in P_VIDEO_CC_PLL0_OUT_MAIN? Yeah, I also saw that.
> 
>> opp failures do you see?
> 
> Only:
> 
> [    9.306006] qcom-iris aa00000.video-codec: dev_pm_opp_set_rate:
> failed to find OPP for freq 630000000 (-34)
> [    9.316078] qcom-iris aa00000.video-codec: power on failed
> [    9.322001] qcom-iris aa00000.video-codec: core init failed

But I misunderstood you - I thought you want to replace 630, to match
downstream driver. If just added, then it's fine.

Best regards,
Krzysztof

Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Krzysztof Kozlowski]

On 12/08/2025 16:45, Krzysztof Kozlowski wrote:
>>> Weird, there's an entry in the frequency table for it (well, * 3 the
>>> rate) and it comes out of the same PLL as other ones.. what sort of
>>
>> You mean freq_tbl in P_VIDEO_CC_PLL0_OUT_MAIN? Yeah, I also saw that.
>>
>>> opp failures do you see?
>>
>> Only:
>>
>> [    9.306006] qcom-iris aa00000.video-codec: dev_pm_opp_set_rate:
>> failed to find OPP for freq 630000000 (-34)
>> [    9.316078] qcom-iris aa00000.video-codec: power on failed
>> [    9.322001] qcom-iris aa00000.video-codec: core init failed
> 
> But I misunderstood you - I thought you want to replace 630, to match
> downstream driver. If just added, then it's fine.

... and to confirm: it works and I double checked it now with frequency
plans, so I will add missing 570.

Best regards,
Krzysztof

Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Dmitry Baryshkov]

On Tue, Aug 12, 2025 at 04:21:12PM +0200, Konrad Dybcio wrote:
> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
> > Add Iris video codec to SM8750 SoC, which comes with significantly
> > different powering up sequence than previous SM8650, thus different
> > clocks and resets.  For consistency keep existing clock and clock-names
> > naming, so the list shares common part.
> > 
> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > 
> > ---
> 
> [...]
> 
> > +			iris_opp_table: opp-table {
> > +				compatible = "operating-points-v2";
> > +
> > +				opp-240000000 {
> > +					opp-hz = /bits/ 64 <240000000>;
> > +					required-opps = <&rpmhpd_opp_low_svs_d1>,
> > +							<&rpmhpd_opp_low_svs_d1>;
> > +				};
> > +
> > +				opp-338000000 {
> > +					opp-hz = /bits/ 64 <338000000>;
> > +					required-opps = <&rpmhpd_opp_low_svs>,
> > +							<&rpmhpd_opp_low_svs>;
> > +				};
> > +
> > +				opp-420000000 {
> > +					opp-hz = /bits/ 64 <420000000>;
> > +					required-opps = <&rpmhpd_opp_svs>,
> > +							<&rpmhpd_opp_svs>;
> > +				};
> > +
> > +				opp-444000000 {
> > +					opp-hz = /bits/ 64 <444000000>;
> > +					required-opps = <&rpmhpd_opp_svs_l1>,
> > +							<&rpmhpd_opp_svs_l1>;
> > +				};
> > +
> > +				opp-533333334 {
> > +					opp-hz = /bits/ 64 <533333334>;
> > +					required-opps = <&rpmhpd_opp_nom>,
> > +							<&rpmhpd_opp_nom>;
> > +				};
> 
> There's an additional OPP: 570 MHz @ NOM_L1
> 
> +Dmitry, Vikash, please make sure you're OK with the iommu entries

We still don't have a way to describe it other way at this point.

> 
> the other properties look OK
> 
> Konrad

-- 
With best wishes
Dmitry

Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Vikash Garodia]

On 8/12/2025 8:09 PM, Dmitry Baryshkov wrote:
> On Tue, Aug 12, 2025 at 04:21:12PM +0200, Konrad Dybcio wrote:
>> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
>>> Add Iris video codec to SM8750 SoC, which comes with significantly
>>> different powering up sequence than previous SM8650, thus different
>>> clocks and resets.  For consistency keep existing clock and clock-names
>>> naming, so the list shares common part.
>>>
>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>
>>> ---
>>
>> [...]
>>
>>> +			iris_opp_table: opp-table {
>>> +				compatible = "operating-points-v2";
>>> +
>>> +				opp-240000000 {
>>> +					opp-hz = /bits/ 64 <240000000>;
>>> +					required-opps = <&rpmhpd_opp_low_svs_d1>,
>>> +							<&rpmhpd_opp_low_svs_d1>;
>>> +				};
>>> +
>>> +				opp-338000000 {
>>> +					opp-hz = /bits/ 64 <338000000>;
>>> +					required-opps = <&rpmhpd_opp_low_svs>,
>>> +							<&rpmhpd_opp_low_svs>;
>>> +				};
>>> +
>>> +				opp-420000000 {
>>> +					opp-hz = /bits/ 64 <420000000>;
>>> +					required-opps = <&rpmhpd_opp_svs>,
>>> +							<&rpmhpd_opp_svs>;
>>> +				};
>>> +
>>> +				opp-444000000 {
>>> +					opp-hz = /bits/ 64 <444000000>;
>>> +					required-opps = <&rpmhpd_opp_svs_l1>,
>>> +							<&rpmhpd_opp_svs_l1>;
>>> +				};
>>> +
>>> +				opp-533333334 {
>>> +					opp-hz = /bits/ 64 <533333334>;
>>> +					required-opps = <&rpmhpd_opp_nom>,
>>> +							<&rpmhpd_opp_nom>;
>>> +				};
>>
>> There's an additional OPP: 570 MHz @ NOM_L1
>>
>> +Dmitry, Vikash, please make sure you're OK with the iommu entries
> 
> We still don't have a way to describe it other way at this point.

I could validate the extended "iommu-map-masks" proposal. Given that we have a
new binding for SM8750 [1] , does it make sense to add iommus min/max as [1,5] ?
such that later if new property is introduced "iommu-map-mask", it does not
break ABI.

iommus = <&apps_smmu 0x1940 0>;
iommu-map-masks = <0 &apps_smmu 0x1947 1 0>;

[1] https://lore.kernel.org/all/20250804-sm8750-iris-v2-1-6d78407f8078@linaro.org/

Regards,
Vikash
> 
>>
>> the other properties look OK
>>
>> Konrad
> 

Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Dmitry Baryshkov]

On Tue, Aug 12, 2025 at 09:01:36PM +0530, Vikash Garodia wrote:
> 
> On 8/12/2025 8:09 PM, Dmitry Baryshkov wrote:
> > On Tue, Aug 12, 2025 at 04:21:12PM +0200, Konrad Dybcio wrote:
> >> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
> >>> Add Iris video codec to SM8750 SoC, which comes with significantly
> >>> different powering up sequence than previous SM8650, thus different
> >>> clocks and resets.  For consistency keep existing clock and clock-names
> >>> naming, so the list shares common part.
> >>>
> >>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >>>
> >>> ---
> >>
> >> [...]
> >>
> >>> +			iris_opp_table: opp-table {
> >>> +				compatible = "operating-points-v2";
> >>> +
> >>> +				opp-240000000 {
> >>> +					opp-hz = /bits/ 64 <240000000>;
> >>> +					required-opps = <&rpmhpd_opp_low_svs_d1>,
> >>> +							<&rpmhpd_opp_low_svs_d1>;
> >>> +				};
> >>> +
> >>> +				opp-338000000 {
> >>> +					opp-hz = /bits/ 64 <338000000>;
> >>> +					required-opps = <&rpmhpd_opp_low_svs>,
> >>> +							<&rpmhpd_opp_low_svs>;
> >>> +				};
> >>> +
> >>> +				opp-420000000 {
> >>> +					opp-hz = /bits/ 64 <420000000>;
> >>> +					required-opps = <&rpmhpd_opp_svs>,
> >>> +							<&rpmhpd_opp_svs>;
> >>> +				};
> >>> +
> >>> +				opp-444000000 {
> >>> +					opp-hz = /bits/ 64 <444000000>;
> >>> +					required-opps = <&rpmhpd_opp_svs_l1>,
> >>> +							<&rpmhpd_opp_svs_l1>;
> >>> +				};
> >>> +
> >>> +				opp-533333334 {
> >>> +					opp-hz = /bits/ 64 <533333334>;
> >>> +					required-opps = <&rpmhpd_opp_nom>,
> >>> +							<&rpmhpd_opp_nom>;
> >>> +				};
> >>
> >> There's an additional OPP: 570 MHz @ NOM_L1
> >>
> >> +Dmitry, Vikash, please make sure you're OK with the iommu entries
> > 
> > We still don't have a way to describe it other way at this point.
> 
> I could validate the extended "iommu-map-masks" proposal. Given that we have a

Was it posted? If not, let's get it ASAP.

> new binding for SM8750 [1] , does it make sense to add iommus min/max as [1,5] ?

Why [1, 5]? It should be [1, 2] or just [1, 1] + your proposal.

> such that later if new property is introduced "iommu-map-mask", it does not
> break ABI.
> 
> iommus = <&apps_smmu 0x1940 0>;
> iommu-map-masks = <0 &apps_smmu 0x1947 1 0>;
> 
> [1] https://lore.kernel.org/all/20250804-sm8750-iris-v2-1-6d78407f8078@linaro.org/
> 
> Regards,
> Vikash
> > 
> >>
> >> the other properties look OK
> >>
> >> Konrad
> > 

-- 
With best wishes
Dmitry

Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Vikash Garodia]

On 8/14/2025 12:11 AM, Dmitry Baryshkov wrote:
> On Tue, Aug 12, 2025 at 09:01:36PM +0530, Vikash Garodia wrote:
>>
>> On 8/12/2025 8:09 PM, Dmitry Baryshkov wrote:
>>> On Tue, Aug 12, 2025 at 04:21:12PM +0200, Konrad Dybcio wrote:
>>>> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
>>>>> Add Iris video codec to SM8750 SoC, which comes with significantly
>>>>> different powering up sequence than previous SM8650, thus different
>>>>> clocks and resets.  For consistency keep existing clock and clock-names
>>>>> naming, so the list shares common part.
>>>>>
>>>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>>>
>>>>> ---
>>>>
>>>> [...]
>>>>
>>>>> +			iris_opp_table: opp-table {
>>>>> +				compatible = "operating-points-v2";
>>>>> +
>>>>> +				opp-240000000 {
>>>>> +					opp-hz = /bits/ 64 <240000000>;
>>>>> +					required-opps = <&rpmhpd_opp_low_svs_d1>,
>>>>> +							<&rpmhpd_opp_low_svs_d1>;
>>>>> +				};
>>>>> +
>>>>> +				opp-338000000 {
>>>>> +					opp-hz = /bits/ 64 <338000000>;
>>>>> +					required-opps = <&rpmhpd_opp_low_svs>,
>>>>> +							<&rpmhpd_opp_low_svs>;
>>>>> +				};
>>>>> +
>>>>> +				opp-420000000 {
>>>>> +					opp-hz = /bits/ 64 <420000000>;
>>>>> +					required-opps = <&rpmhpd_opp_svs>,
>>>>> +							<&rpmhpd_opp_svs>;
>>>>> +				};
>>>>> +
>>>>> +				opp-444000000 {
>>>>> +					opp-hz = /bits/ 64 <444000000>;
>>>>> +					required-opps = <&rpmhpd_opp_svs_l1>,
>>>>> +							<&rpmhpd_opp_svs_l1>;
>>>>> +				};
>>>>> +
>>>>> +				opp-533333334 {
>>>>> +					opp-hz = /bits/ 64 <533333334>;
>>>>> +					required-opps = <&rpmhpd_opp_nom>,
>>>>> +							<&rpmhpd_opp_nom>;
>>>>> +				};
>>>>
>>>> There's an additional OPP: 570 MHz @ NOM_L1
>>>>
>>>> +Dmitry, Vikash, please make sure you're OK with the iommu entries
>>>
>>> We still don't have a way to describe it other way at this point.
>>
>> I could validate the extended "iommu-map-masks" proposal. Given that we have a
> 
> Was it posted? If not, let's get it ASAP.

iommu-range (+Prakash) is a WIP, which is needed alognwith iommu-map-mask.

> 
>> new binding for SM8750 [1] , does it make sense to add iommus min/max as [1,5] ?
> 
> Why [1, 5]? It should be [1, 2] or just [1, 1] + your proposal.

[1,2] should be good for the iris device and remaining SIDs can be covered with
device allocated dynamically via iommu-map-mask proposal

> 
>> such that later if new property is introduced "iommu-map-mask", it does not
>> break ABI.
>>
>> iommus = <&apps_smmu 0x1940 0>;
>> iommu-map-masks = <0 &apps_smmu 0x1947 1 0>;
>>
>> [1] https://lore.kernel.org/all/20250804-sm8750-iris-v2-1-6d78407f8078@linaro.org/
>>
>> Regards,
>> Vikash
>>>
>>>>
>>>> the other properties look OK
>>>>
>>>> Konrad
>>>
> 

[PATCH DO NOT MERGE RFC v2 2/3] arm64: dts: qcom: sm8750-mtp: Enable Iris codec

[Krzysztof Kozlowski]

Enable on SM8750 MTP the Iris video codec for accelerated video
encoding/decoding.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

---

Do not merge because firmware (hard-coded in the driver) is not released.

For Rob's bot reports:

qcom,sm8750-videocc bindings and clock headers dependency (will fail
build):
https://lore.kernel.org/all/20241206-sm8750_videocc-v1-0-5da6e7eea2bd@quicinc.com/

qcom,sm8750-iris bindings:
https://lore.kernel.org/r/20250804-sm8750-iris-v2-0-6d78407f8078@linaro.org
---
 arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
index 75cfbb510be57a1ab8cb3d870b5c34d3baa53c70..4c155b731a68138154f66fdb0d0e6db5e47adf3c 100644
--- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
@@ -812,6 +812,10 @@ vreg_l7n_3p3: ldo7 {
 	};
 };
 
+&iris {
+	status = "okay";
+};
+
 &lpass_vamacro {
 	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
 	pinctrl-names = "default";

-- 
2.48.1

Re: [PATCH DO NOT MERGE RFC v2 2/3] arm64: dts: qcom: sm8750-mtp: Enable Iris codec

[Dmitry Baryshkov]

On Wed, Aug 06, 2025 at 02:38:31PM +0200, Krzysztof Kozlowski wrote:
> Enable on SM8750 MTP the Iris video codec for accelerated video
> encoding/decoding.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> ---
> 
> Do not merge because firmware (hard-coded in the driver) is not released.

I don't think we have been delaying enablement of the hardware for these
reasons. The user might have other ways to get the firmware (or to
disable the device) in DT.

-- 
With best wishes
Dmitry

Re: [PATCH DO NOT MERGE RFC v2 2/3] arm64: dts: qcom: sm8750-mtp: Enable Iris codec

[Bjorn Andersson]

On Sat, Aug 09, 2025 at 12:42:16PM +0300, Dmitry Baryshkov wrote:
> On Wed, Aug 06, 2025 at 02:38:31PM +0200, Krzysztof Kozlowski wrote:
> > Enable on SM8750 MTP the Iris video codec for accelerated video
> > encoding/decoding.
> > 
> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > 
> > ---
> > 
> > Do not merge because firmware (hard-coded in the driver) is not released.
> 
> I don't think we have been delaying enablement of the hardware for these
> reasons. The user might have other ways to get the firmware (or to
> disable the device) in DT.
> 

At least with the venus driver, missing firmware would result in
sync_state never happening. I see there's some changes in that behavior
lately, so perhaps this has changed?

But I agree with you that it would be preferable to deal with this
shortcoming in the implementation, rather than holding back the hardware
description.

Regards,
Bjorn

> -- 
> With best wishes
> Dmitry

[PATCH DO NOT MERGE RFC v2 3/3] arm64: dts: qcom: sm8750-qrd: Enable Iris codec

[Krzysztof Kozlowski]

Enable on SM8750 QRD the Iris video codec for accelerated video
encoding/decoding.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

---

Do not merge because firmware (hard-coded in the driver) is not released.

For Rob's bot reports:

qcom,sm8750-videocc bindings and clock headers dependency (will fail
build):
https://lore.kernel.org/all/20241206-sm8750_videocc-v1-0-5da6e7eea2bd@quicinc.com/

qcom,sm8750-iris bindings:
https://lore.kernel.org/r/20250804-sm8750-iris-v2-0-6d78407f8078@linaro.org
---
 arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
index 13c7b9664c89cffb68a1f941c16b30074816af8b..369623f8e4c921e99532d5e22fe9f0049746ebaf 100644
--- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
@@ -813,6 +813,10 @@ vreg_l7n_3p3: ldo7 {
 	};
 };
 
+&iris {
+	status = "okay";
+};
+
 &pm8550_flash {
 	status = "okay";
 

-- 
2.48.1

Re: [PATCH RFC v2 0/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Rob Herring (Arm)]

On Wed, 06 Aug 2025 14:38:29 +0200, Krzysztof Kozlowski wrote:
> Hi,
> 
> Changes in v2:
> - Patch #1: Add RPMHPD_MXC (Konrad)
> - Link to v1: https://lore.kernel.org/r/20250714-b4-sm8750-iris-dts-v1-0-93629b246d2e@linaro.org
> 
> RFC because depends on old series (6 months old!) which received
> feedback and nothing happened since that time.  I assume author
> abandoned that series, but unfortunately unmerged bindings for
> qcom,sm8750-videocc block this patchset:
> https://lore.kernel.org/all/20241206-sm8750_videocc-v1-0-5da6e7eea2bd@quicinc.com/
> 
> The bindings for new compatible qcom,sm8750-iris:
> https://lore.kernel.org/r/20250804-sm8750-iris-v2-0-6d78407f8078@linaro.org
> 
> Best regards,
> Krzysztof
> 
> ---
> Krzysztof Kozlowski (3):
>       arm64: dts: qcom: sm8750: Add Iris VPU v3.5
>       [DO NOT MERGE] arm64: dts: qcom: sm8750-mtp: Enable Iris codec
>       [DO NOT MERGE] arm64: dts: qcom: sm8750-qrd: Enable Iris codec
> 
>  arch/arm64/boot/dts/qcom/sm8750-mtp.dts |   4 ++
>  arch/arm64/boot/dts/qcom/sm8750-qrd.dts |   4 ++
>  arch/arm64/boot/dts/qcom/sm8750.dtsi    | 113 ++++++++++++++++++++++++++++++++
>  3 files changed, 121 insertions(+)
> ---
> base-commit: 709a73d51f11d75ee2aee4f690e4ecd8bc8e9bf3
> change-id: 20250714-b4-sm8750-iris-dts-ebdb5dc4ee27
> prerequisite-message-id: 20241206-sm8750_videocc-v1-0-5da6e7eea2bd@quicinc.com
> prerequisite-patch-id: ada17af875101625f7754335fabc909c8ab9cd20
> prerequisite-patch-id: 3cb47a7c47cd96e02b5a4a05490088541f97c629
> prerequisite-patch-id: 8c77b8e0c611b5e28086a456157940d773b323ab
> 
> Best regards,
> --
> Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: using specified base-commit 709a73d51f11d75ee2aee4f690e4ecd8bc8e9bf3
 Deps: looking for dependencies matching 3 patch-ids
 Deps: Applying prerequisite patch: [PATCH 1/3] clk: qcom: branch: Extend invert logic for branch2 mem clocks
 Deps: Applying prerequisite patch: [PATCH 2/3] dt-bindings: clock: qcom: Add SM8750 video clock controller
 Deps: Applying prerequisite patch: [PATCH 3/3] clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250806-b4-sm8750-iris-dts-v2-0-2ce197525eed@linaro.org:

arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: /soc@0/video-codec@aa00000: failed to match any schema with compatible: ['qcom,sm8750-iris']
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: clock-controller@aaf0000 (qcom,sm8750-videocc): 'required-opps' is a required property
	from schema $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: /soc@0/video-codec@aa00000: failed to match any schema with compatible: ['qcom,sm8750-iris']
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: clock-controller@aaf0000 (qcom,sm8750-videocc): 'required-opps' is a required property
	from schema $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#

Re: [PATCH RFC v2 0/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Bjorn Andersson]

On Wed, Aug 06, 2025 at 09:40:29AM -0500, Rob Herring (Arm) wrote:
> On Wed, 06 Aug 2025 14:38:29 +0200, Krzysztof Kozlowski wrote:
[..]
> arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: /soc@0/video-codec@aa00000: failed to match any schema with compatible: ['qcom,sm8750-iris']
> arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: clock-controller@aaf0000 (qcom,sm8750-videocc): 'required-opps' is a required property
> 	from schema $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#

Can anyone help me understand why required-opps is a required property
in the videocc binding?

Is there a valid level below "low_svs" that is otherwise selected, but
insufficient to keep the clock controller ticking?

Regards,
Bjorn

Re: [PATCH RFC v2 0/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

[Neil Armstrong]

On 11/08/2025 18:15, Bjorn Andersson wrote:
> On Wed, Aug 06, 2025 at 09:40:29AM -0500, Rob Herring (Arm) wrote:
>> On Wed, 06 Aug 2025 14:38:29 +0200, Krzysztof Kozlowski wrote:
> [..]
>> arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: /soc@0/video-codec@aa00000: failed to match any schema with compatible: ['qcom,sm8750-iris']
>> arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: clock-controller@aaf0000 (qcom,sm8750-videocc): 'required-opps' is a required property
>> 	from schema $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
> 
> Can anyone help me understand why required-opps is a required property
> in the videocc binding?

Tee DT changes are to be picked, see https://lore.kernel.org/all/0a6baf09-b1b8-4573-b53d-574838efd9ec@quicinc.com/

I asked for them to be re-sent, but no...

Neil

> 
> Is there a valid level below "low_svs" that is otherwise selected, but
> insufficient to keep the clock controller ticking?
> 
> Regards,
> Bjorn