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Tue, 26 Nov 2024 02:03:54 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AQ23rbd027020 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 26 Nov 2024 02:03:53 GMT Received: from [10.110.75.163] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 25 Nov 2024 18:03:52 -0800 Message-ID: <784a7813-b024-452e-8d7e-8cbaea761bcd@quicinc.com> Date: Mon, 25 Nov 2024 18:03:52 -0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] drm/msm/mdss: define bitfields for the UBWC_STATIC register To: Dmitry Baryshkov , Rob Clark , Sean Paul , Marijn Suijten , Connor Abbott , David Airlie , Simona Vetter CC: , , , References: <20241123-msm-mdss-ubwc-v2-0-41344bc6ef9c@linaro.org> <20241123-msm-mdss-ubwc-v2-1-41344bc6ef9c@linaro.org> Content-Language: en-US From: Abhinav Kumar In-Reply-To: <20241123-msm-mdss-ubwc-v2-1-41344bc6ef9c@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4og3NpsBxv4WY-Z7NQ7DQwu_3JEWZ0AQ X-Proofpoint-ORIG-GUID: 4og3NpsBxv4WY-Z7NQ7DQwu_3JEWZ0AQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 mlxlogscore=999 clxscore=1011 mlxscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411260015 On 11/22/2024 9:44 PM, Dmitry Baryshkov wrote: > Rather than hand-coding UBWC_STATIC value calculation, define > corresponding bitfields and use them to setup the register value. > > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/msm_mdss.c | 38 +++++++++++++++----------- > drivers/gpu/drm/msm/msm_mdss.h | 3 +- > drivers/gpu/drm/msm/registers/display/mdss.xml | 11 +++++++- > 3 files changed, 34 insertions(+), 18 deletions(-) > > > diff --git a/drivers/gpu/drm/msm/registers/display/mdss.xml b/drivers/gpu/drm/msm/registers/display/mdss.xml > index ac85caf1575c7908bcf68f0249da38dccf4f07b6..b6f93984928522a35a782cbad9de006eac225725 100644 > --- a/drivers/gpu/drm/msm/registers/display/mdss.xml > +++ b/drivers/gpu/drm/msm/registers/display/mdss.xml > @@ -21,7 +21,16 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> > > > > - > + > + > + > + > + > + MIN_ACC_LEN OR MALSIZE has 2 bits , bits 8 and 9. But bit 9 is unused today. Hence we were using it as a 1 or 0 today. Its unused on all the chipsets I checked. Do you want to continue using the same way or correct this?