From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF0BAC7EE29 for ; Fri, 9 Jun 2023 15:40:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232115AbjFIPj6 (ORCPT ); Fri, 9 Jun 2023 11:39:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241835AbjFIPjg (ORCPT ); Fri, 9 Jun 2023 11:39:36 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5D5A835AC; Fri, 9 Jun 2023 08:39:33 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 88FB6AB6; Fri, 9 Jun 2023 08:40:18 -0700 (PDT) Received: from [10.57.85.120] (unknown [10.57.85.120]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 45C7D3F663; Fri, 9 Jun 2023 08:39:30 -0700 (PDT) Message-ID: <78995241-826f-bf42-9d4b-9ab7c9c9bf7d@arm.com> Date: Fri, 9 Jun 2023 16:39:29 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 0/3] arm64: dts: qcom: sa8775p: Add interconnect to SMMU Content-Language: en-GB To: Dmitry Baryshkov , Konrad Dybcio Cc: Parikshit Pareek , Will Deacon , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Manivannan Sadhasivam , Marijn Suijten , Adam Skladowski , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, "linux-kernel @ vger . kernel . org Prasanna Kumar" , Shazad Hussain References: <20230609054141.18938-1-quic_ppareek@quicinc.com> <79206b05-674b-1f6c-6eb1-ed45e6bd5637@linaro.org> <20230609125631.GA29252@hu-ppareek-blr.qualcomm.com> <2881f374-70e2-0057-f43e-7be12d32ae22@arm.com> From: Robin Murphy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2023-06-09 15:56, Dmitry Baryshkov wrote: > On Fri, 9 Jun 2023 at 17:52, Konrad Dybcio wrote: >> >> >> >> On 9.06.2023 16:45, Robin Murphy wrote: >>> On 2023-06-09 13:56, Parikshit Pareek wrote: >>>> On Fri, Jun 09, 2023 at 10:52:26AM +0200, Konrad Dybcio wrote: >>>>> >>>>> >>>>> On 9.06.2023 07:41, Parikshit Pareek wrote: >>>>>> Some qcom SoCs have SMMUs, which need the interconnect bandwidth to be >>>>>> This series introduce the due support for associated interconnect, and >>>>>> setting of the due interconnect-bandwidth. Setting due interconnect >>>>>> bandwidth is needed to avoid the issues like [1], caused by not having >>>>>> due clock votes(indirectly dependent upon interconnect bandwidth). >>>>> >>>>> [1] ??? >>>> >>>> My bad. Intended to mention following: >>>> https://lore.kernel.org/linux-arm-msm/20230418165224.vmok75fwcjqdxspe@echanude/ >>> >>> This sounds super-dodgy - do you really have to rely on configuration of the interconnect path from the SMMU's pagetable walker to RAM to keep a completely different interconnect path clocked for the CPU to access SMMU registers? You can't just request the programming interface clock directly like on other SoCs? >> On Qualcomm platforms, particularly so with the more recent ones, some >> clocks are managed by various remote cores. Half of what the interconnect >> infra does on these SoCs is telling one such core to change the internally >> managed clock's rate based on the requested bw. > > But enabling PCIe interconnect to keep SMMU working sounds strange to > me too. Does the fault come from some outstanding PCIe transaction? The "Injecting instruction/data abort to VM 3" message from the hypervisor implies that it is the access to SMMU_CR0 from arm_smmu_shutdown() that's blown up. I can even believe that the SMMU shares some clocks with the PCIe interconnect, given that its TBU must be *in* that path from PCIe to memory, at least. However I would instinctively expect the abstraction layers above to have some notion of distinct votes for "CPU wants to access SMMU" vs. "SMMU/PCIe wants to access RAM", given that the latter is liable to need to enable more than the former if the clock/power gating is as fine-grained as previous SoCs seem to have been. But maybe my hunch is wrong and this time everything's just in one big clock domain. I don't know. I'm just here to ask questions to establish whether this really is the most correct abstraction or just a lazy bodge to avoid doing the proper thing in some other driver. Thanks, Robin.