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From: Krishna Chaitanya Chundru <quic_krichai@quicinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	Konrad Dybcio <konradybcio@kernel.org>
Cc: "Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com,
	quic_vbadigan@quicinc.com,
	"Bjorn Andersson" <andersson@kernel.org>
Subject: Re: [PATCH v3 2/4] PCI: of: Add API to retrieve equalization presets from device tree
Date: Mon, 23 Dec 2024 22:13:29 +0530	[thread overview]
Message-ID: <7bc9f3f2-851c-3703-39b4-fea93d10bd7f@quicinc.com> (raw)
In-Reply-To: <wjk32haduzgiea676mamqdr6mhbmm3rrb6eyhzghqpczjuiazx@ipik3jhjzmhz>



On 12/23/2024 8:56 PM, Dmitry Baryshkov wrote:
> On Mon, Dec 23, 2024 at 08:02:23PM +0530, Krishna Chaitanya Chundru wrote:
>>
>>
>> On 12/23/2024 5:17 PM, Dmitry Baryshkov wrote:
>>> On Mon, Dec 23, 2024 at 12:21:15PM +0530, Krishna Chaitanya Chundru wrote:
>>>> PCIe equalization presets are predefined settings used to optimize
>>>> signal integrity by compensating for signal loss and distortion in
>>>> high-speed data transmission.
>>>>
>>>> As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates
>>>> of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to
>>>> configure lane equalization presets for each lane to enhance the PCIe
>>>> link reliability. Each preset value represents a different combination
>>>> of pre-shoot and de-emphasis values. For each data rate, different
>>>> registers are defined: for 8.0 GT/s, registers are defined in section
>>>> 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has
>>>> an extra receiver preset hint, requiring 16 bits per lane, while the
>>>> remaining data rates use 8 bits per lane.
>>>>
>>>> Based on the number of lanes and the supported data rate, this function
>>>> reads the device tree property and stores in the presets structure.
>>>>
>>>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>>>> ---
>>>>    drivers/pci/of.c  | 45 +++++++++++++++++++++++++++++++++++++++++++++
>>>>    drivers/pci/pci.h | 17 +++++++++++++++--
>>>>    2 files changed, 60 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
>>>> index dacea3fc5128..99e0e7ae12e9 100644
>>>> --- a/drivers/pci/of.c
>>>> +++ b/drivers/pci/of.c
>>>> @@ -826,3 +826,48 @@ u32 of_pci_get_slot_power_limit(struct device_node *node,
>>>>    	return slot_power_limit_mw;
>>>>    }
>>>>    EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit);
>>>> +
>>>
>>> kerneldoc? Define who should free the memory and how.
>>>
>> I will update this in next series.
>> as we are allocating using devm_kzalloc it should be freed on driver
>> detach, as no special freeing is required.
>>>> +int of_pci_get_equalization_presets(struct device *dev,
>>>> +				    struct pci_eq_presets *presets,
>>>> +				    int num_lanes)
>>>> +{
>>>> +	char name[20];
>>>> +	void **preset;
>>>> +	void *temp;
>>>> +	int ret;
>>>> +
>>>> +	if (of_property_present(dev->of_node, "eq-presets-8gts")) {
>>>> +		presets->eq_presets_8gts = devm_kzalloc(dev, sizeof(u16) * num_lanes, GFP_KERNEL);
>>>> +		if (!presets->eq_presets_8gts)
>>>> +			return -ENOMEM;
>>>> +
>>>> +		ret = of_property_read_u16_array(dev->of_node, "eq-presets-8gts",
>>>> +						 presets->eq_presets_8gts, num_lanes);
>>>> +		if (ret) {
>>>> +			dev_err(dev, "Error reading eq-presets-8gts %d\n", ret);
>>>> +			return ret;
>>>> +		}
>>>> +	}
>>>> +
>>>> +	for (int i = 1; i < sizeof(struct pci_eq_presets) / sizeof(void *); i++) {
>>>> +		snprintf(name, sizeof(name), "eq-presets-%dgts", 8 << i);
>>>> +		if (of_property_present(dev->of_node, name)) {
>>>> +			temp = devm_kzalloc(dev, sizeof(u8) * num_lanes, GFP_KERNEL);
>>>> +			if (!temp)
>>>> +				return -ENOMEM;
>>>> +
>>>> +			ret = of_property_read_u8_array(dev->of_node, name,
>>>> +							temp, num_lanes);
>>>> +			if (ret) {
>>>> +				dev_err(dev, "Error %s %d\n", name, ret);
>>>> +				return ret;
>>>> +			}
>>>> +
>>>> +			preset = (void **)((u8 *)presets + i * sizeof(void *));
>>>
>>> Ugh.
>>>
>> I was trying iterate over each element on the structure as presets holds the
>> starting address of the structure and to that we are adding size of the void
>> * point to go to each element. I did this way to reduce the
>> redundant code to read all the gts which has same way of storing the data
>> from the device tree. I will add comments here in the next series.
> 
> Please rewrite this in a cleaner way. The code shouldn't raise
> questions.
> 
>>>> +			*preset = temp;
>>>> +		}
>>>> +	}
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +EXPORT_SYMBOL_GPL(of_pci_get_equalization_presets);
>>>> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
>>>> index 14d00ce45bfa..82362d58bedc 100644
>>>> --- a/drivers/pci/pci.h
>>>> +++ b/drivers/pci/pci.h
>>>> @@ -731,7 +731,12 @@ static inline u64 pci_rebar_size_to_bytes(int size)
>>>>    }
>>>>    struct device_node;
>>>> -
>>>> +struct pci_eq_presets {
>>>> +	void *eq_presets_8gts;
>>>> +	void *eq_presets_16gts;
>>>> +	void *eq_presets_32gts;
>>>> +	void *eq_presets_64gts;
>>>
>>> Why are all of those void*? 8gts is u16*, all other are u8*.
>>>
>> To have common parsing logic I moved them to void*, as these are pointers
>> actual memory is allocated by of_pci_get_equalization_presets()
>> based upon the gts these should not give any issues.
> 
> Please, don't. They have types. void pointers are for the opaque data.
> 
ok.

I think then better to use v1 patch 
https://lore.kernel.org/all/20241116-presets-v1-2-878a837a4fee@quicinc.com/

konrad, any objection on using v1 as that will be cleaner way even if we
have some repetitive code.

- Krishna Chaitanya.

>>>> +};
>>>
>>> Empty lines before and after the struct definition.
>>>
>> ack.
>>
>> - Krishna Chaitanya.
>>>>    #ifdef CONFIG_OF
>>>>    int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
>>>>    int of_get_pci_domain_nr(struct device_node *node);
>>>> @@ -746,7 +751,9 @@ void pci_set_bus_of_node(struct pci_bus *bus);
>>>>    void pci_release_bus_of_node(struct pci_bus *bus);
>>>>    int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
>>>> -
>>>> +int of_pci_get_equalization_presets(struct device *dev,
>>>> +				    struct pci_eq_presets *presets,
>>>> +				    int num_lanes);
>>>
>>> Keep the empty line.
>>>
>>>>    #else
>>>>    static inline int
>>>>    of_pci_parse_bus_range(struct device_node *node, struct resource *res)
>>>> @@ -793,6 +800,12 @@ static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_br
>>>>    	return 0;
>>>>    }
>>>> +static inline int of_pci_get_equalization_presets(struct device *dev,
>>>> +						  struct pci_eq_presets *presets,
>>>> +						  int num_lanes)
>>>> +{
>>>> +	return 0;
>>>> +}
>>>>    #endif /* CONFIG_OF */
>>>>    struct of_changeset;
>>>>
>>>> -- 
>>>> 2.34.1
>>>>
>>>
> 

  reply	other threads:[~2024-12-23 16:43 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-23  6:51 [PATCH v3 0/4] PCI: dwc: Add support for configuring lane equalization presets Krishna Chaitanya Chundru
2024-12-23  6:51 ` [PATCH v3 1/4] arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties Krishna Chaitanya Chundru
2024-12-23 11:36   ` Konrad Dybcio
2024-12-23 14:35     ` Krishna Chaitanya Chundru
2024-12-23  6:51 ` [PATCH v3 2/4] PCI: of: Add API to retrieve equalization presets from device tree Krishna Chaitanya Chundru
2024-12-23 11:47   ` Dmitry Baryshkov
2024-12-23 14:32     ` Krishna Chaitanya Chundru
2024-12-23 15:26       ` Dmitry Baryshkov
2024-12-23 16:43         ` Krishna Chaitanya Chundru [this message]
2024-12-23 18:30           ` Dmitry Baryshkov
2024-12-24  9:17             ` Krishna Chaitanya Chundru
2024-12-24  9:55               ` Dmitry Baryshkov
2024-12-24 10:35                 ` Krishna Chaitanya Chundru
2024-12-24 10:57                   ` Dmitry Baryshkov
2024-12-30 13:41                     ` Konrad Dybcio
2024-12-31  4:38                       ` Krishna Chaitanya Chundru
2025-01-03 11:43                         ` Konrad Dybcio
2024-12-23  6:51 ` [PATCH v3 3/4] PCI: dwc: Improve handling of PCIe lane configuration Krishna Chaitanya Chundru
2024-12-23  6:51 ` [PATCH v3 4/4] PCI: dwc: Add support for configuring lane equalization presets Krishna Chaitanya Chundru

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