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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDIyMDE1NSBTYWx0ZWRfX01wDKAP/QaHQ VPT6C46vqSU1/dP/kUkz9CBjZ3/Ub5L6d9+bN4hsB+ofq/uc8iTZoMi1uVzbrk2FjOe+Exr/so1 M0+hcJrmxeX5+RVN30EglvwJXpbGUDoewWLIAnmbXQ66njwOCSj3Xwom0w4XRs3rG+wEbpE/W8z yZWLWBREnUJbpp6u+IwAOe9mMiayugGzEUGvQ80dnRc79U3OTViT7uT7OhZNhObzRHaqnmV13+L wdSQtjPWd9EYA3TUcixwrMDDpFo0V1UoB5hQBm21VOQes7LaiE51xVrriXcPLyLKaSMWKHN1y8R oLrtlbh79fMzPY/W2D4K3jVy2OQzxPjXyiSy8heNyXgA/JWyZxo82vKYhU3UvMCRTeZko5NRFce KRrlv8lpUtEWmLPsqMW8C/SpR4QGcA== X-Authority-Analysis: v=2.4 cv=Uotu9uwB c=1 sm=1 tr=0 ts=68fb8bcf cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=Kgau_Mukr_2Uqyo6pRUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: 1U7kj86kZCHTllmIN5K-Vnfm9bcZQOj9 X-Proofpoint-ORIG-GUID: 1U7kj86kZCHTllmIN5K-Vnfm9bcZQOj9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-24_02,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510220155 On 10/24/2025 6:46 PM, Rob Clark wrote: > On Fri, Oct 24, 2025 at 12:55 AM Konrad Dybcio > wrote: >> >> On 10/24/25 12:57 AM, Akhil P Oommen wrote: >>> On 10/22/2025 8:43 PM, Konrad Dybcio wrote: >>>> On 10/17/25 7:08 PM, Akhil P Oommen wrote: >>>>> From: Jie Zhang >>>>> >>>>> Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets. >>>>> A612 falls under ADRENO_6XX_GEN1 family and is a cut down version >>>>> of A615 GPU. >>>>> >>>>> A612 has a new IP called Reduced Graphics Management Unit or RGMU >>>>> which is a small state machine which helps to toggle GX GDSC >>>>> (connected to CX rail) to implement IFPC feature. It doesn't support >>>>> any other features of a full fledged GMU like clock control, resource >>>>> voting to rpmh etc. So we need linux clock driver support like other >>>>> gmu-wrapper implementations to control gpu core clock and gpu GX gdsc. >>>>> This patch skips RGMU core initialization and act more like a >>>>> gmu-wrapper case. >>>>> >>>>> Co-developed-by: Akhil P Oommen >>>>> Signed-off-by: Jie Zhang >>>>> Signed-off-by: Akhil P Oommen >>>>> --- >>>> >>>> [...] >>>> >>>>> @@ -350,12 +350,18 @@ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = { >>>>> /* Trigger a OOB (out of band) request to the GMU */ >>>>> int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) >>>>> { >>>>> + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); >>>>> + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; >>>>> int ret; >>>>> u32 val; >>>>> int request, ack; >>>>> >>>>> WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); >>>>> >>>>> + /* Skip OOB calls since RGMU is not enabled */ >>>> >>>> "RGMU doesn't handle OOB calls" >>> >>> Technically RGMU can handle OOB calls. But we are not initializing rgmu. >> >> Oh, I glossed over that.. >> >> IIRC the reason we delayed 612 support in the past was to make sure >> that the RGMU FW is consumed, so that runtime requirements don't >> suddenly change one day. >> >> If you have no interest/way in getting it wholly supported right now, >> can you at least make sure that the driver requests the firmware and >> exits if it's absent? > > adreno_load_gpu() calls adreno_load_fw() first thing, and will bail if > gmu fw is missing. (zap fw is a bit more awkward since that could > come from dt or device table.) Correct. And RGMU firmware is available in linux-firmware repo. -Akhil. > > BR, > -R