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[83.9.29.26]) by smtp.gmail.com with ESMTPSA id v12-20020ac2560c000000b004fb64600e5dsm201639lfd.219.2023.07.06.04.00.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Jul 2023 04:00:01 -0700 (PDT) Message-ID: <7d335f1d-ef2c-ffe6-e364-c3dc47479929@linaro.org> Date: Thu, 6 Jul 2023 12:59:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Content-Language: en-US To: Imran Shaik , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Taniya Das , Melody Olvera , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jagadeesh Kona , Satya Priya Kakitapalli , Ajit Pandey References: <20230628092837.3090801-1-quic_imrashai@quicinc.com> <20230628092837.3090801-4-quic_imrashai@quicinc.com> <05f3459f-a2cd-3e4d-bbc6-f0109dbae778@quicinc.com> From: Konrad Dybcio Subject: Re: [PATCH V2 3/5] clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version In-Reply-To: <05f3459f-a2cd-3e4d-bbc6-f0109dbae778@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 6.07.2023 12:51, Imran Shaik wrote: > > > On 6/28/2023 4:36 PM, Konrad Dybcio wrote: >> On 28.06.2023 11:28, Imran Shaik wrote: >>> Add support for gcc_ddrss_ecpri_gsi_clk and update the GCC clkref clocks >>> as per the latest hardware version of QDU1000 and QRU100 SoCs. >>> >>> Co-developed-by: Taniya Das >>> Signed-off-by: Taniya Das >>> Signed-off-by: Imran Shaik >>> --- [...] >>>           .enable_reg = 0x9c004, >>>           .enable_mask = BIT(0), >>>           .hw.init = &(const struct clk_init_data) { >>>               .name = "gcc_pcie_0_clkref_en", >>> -            .ops = &clk_branch_ops, >>> +            .ops = &clk_branch2_ops, >> This sounds like a separate fix, clk_branch_ops seems to only concern >> 10+yo chips. >> >> Konrad > > Sure, will split this patch and push the next series. One more nit, I noticed that a lot of QUIC folks respond to the comments to their revision-N and send revision-(N+1) like 5 seconds later.. This maybe does not concern this message, as all you did is said "ok willfix", but if you have some sort of a company-wide "upstream best practices" board, you may add something like "wait a bit to let others respond to your email" Konrad > > Thanks, > Imran > >>>           }, >>>       }, >>>   }; >>> @@ -2274,14 +2293,13 @@ static struct clk_branch gcc_tsc_etu_clk = { >>>     static struct clk_branch gcc_usb2_clkref_en = { >>>       .halt_reg = 0x9c008, >>> -    .halt_bit = 31, >>> -    .halt_check = BRANCH_HALT_ENABLE, >>> +    .halt_check = BRANCH_HALT, >>>       .clkr = { >>>           .enable_reg = 0x9c008, >>>           .enable_mask = BIT(0), >>>           .hw.init = &(const struct clk_init_data) { >>>               .name = "gcc_usb2_clkref_en", >>> -            .ops = &clk_branch_ops, >>> +            .ops = &clk_branch2_ops, >>>           }, >>>       }, >>>   }; >>> @@ -2523,6 +2541,8 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { >>>       [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, >>>       [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, >>>       [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, >>> +    [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, >>> +    [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, >>>   }; >>>     static const struct qcom_reset_map gcc_qdu1000_resets[] = {