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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bdc87890b46sm33705866b.13.2026.05.21.04.16.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 May 2026 04:16:19 -0700 (PDT) Message-ID: <7ea2f2cc-ef11-4727-810c-e32e815bd973@oss.qualcomm.com> Date: Thu, 21 May 2026 13:16:17 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] powercap: qcom: Add SPEL powercap driver To: Manaf Meethalavalappu Pallikunhi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Bjorn Andersson , Konrad Dybcio , Daniel Lezcano Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Gaurav Kohli References: <20260519-qcom_spel_driver_upstream-v1-0-75356d1b7f94@oss.qualcomm.com> <20260519-qcom_spel_driver_upstream-v1-2-75356d1b7f94@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260519-qcom_spel_driver_upstream-v1-2-75356d1b7f94@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIxMDExMiBTYWx0ZWRfX39FVKn5yE1jE vHDK7k3zKVIt7/jiS4F4L5YHBrqeHCsyh2AdTm0jzDyZVXk24bMmNcA+SMAioc1fKG9DPES5KuF 3YOhQgZhHlWQxselAjwU9cDFdoQhEBBabe3E96HlosvfcIIHYbEmNfTtvLdH3M7G0aBdW9gw+XK NPYNagOnS+GAgNvrV0aa4dzmLHCp2attRCPULduqMiPLfY5yadGZ4t9cgjiwhC6LxTsjW1Ofej8 yqXsNielshC7vHvHNfs5N8S+Yl6f6Yxz+TJjU9wneOgVN5dJAxIgPKPq965GZtzD1DCfDP5UV5c jvC33+9100tbVJ9BQTyS766RA292e4MLJOOECXYhRDN+sWhechAAbcX1cupplMRmEEq1+fAIaR5 RM2alcGb393hQY9XlK4PZwT119fDtHPsuJxTgIHlJTDYUqkeLjcoVBCds94zzqsSeePvv6sWQU7 5zLlBJgRYpdN1VwV0wg== X-Authority-Analysis: v=2.4 cv=GYAnWwXL c=1 sm=1 tr=0 ts=6a0ee985 cx=c_pps a=N1BjEkVkxJi3uNfLdpvX3g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=8bRiB-4Q7LyQZs0zT0oA:9 a=QEXdDO2ut3YA:10 a=crWF4MFLhNY0qMRaF8an:22 X-Proofpoint-GUID: 67PqBVbfcjdwzhGnilWdXFTh7SMRC45M X-Proofpoint-ORIG-GUID: 67PqBVbfcjdwzhGnilWdXFTh7SMRC45M X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-21_01,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605210112 On 5/19/26 12:49 PM, Manaf Meethalavalappu Pallikunhi wrote: > The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware > based power monitoring and limiting capabilities for various power > domains including System, SoC, CPU clusters, GPU, and various other > subsystems. > > The driver integrates with the Linux powercap framework, exposing SPEL > capabilities through powercap sysfs interfaces. > > Signed-off-by: Manaf Meethalavalappu Pallikunhi > --- [...] > +/* SPEL register bitmasks */ > +#define ENERGY_STATUS_MASK 0xFFFFFFFF GENMASK(m, n), across the other defines too, please Then, you can drop the _OFFSET defines as FIELD_PREP/GET/MODIFY accessors will derive them from the mask Please also use lowercase hex, file-wide [...] > +/* Constraint configuration */ > +static struct spel_constraint_info constraints[] = { > + /* SYS domain constraints */ > + { 0x10, 0x70, BIT(0), SPEL_DOMAIN_SYS, POWER_LIMIT1 }, > + { 0x14, 0x74, BIT(1), SPEL_DOMAIN_SYS, POWER_LIMIT2 }, > + { 0x18, 0x78, BIT(2), SPEL_DOMAIN_SYS, POWER_LIMIT3 }, > + { 0x1C, 0x7C, BIT(3), SPEL_DOMAIN_SYS, POWER_LIMIT4 }, > + /* SOC domain constraints */ "SoC" > +/* Helper functions */ > +static bool is_pl_valid(struct spel_domain *sd, int pl) > +{ > + if (pl < POWER_LIMIT1 || pl >= NR_POWER_LIMITS) > + return false; > + return sd->pl_name[pl] ? true : false; return !!sd->pl_name[pl] [...] > +static u64 spel_unit_xlate(struct spel_domain *sd, enum unit_type type, > + u64 value, int to_raw) > +{ > + struct spel_system *sp = sd->sp; > + u64 units = 1; > + u64 scale = 1; > + > + switch (type) { > + case POWER_UNIT: > + units = sp->power_unit; > + break; > + case ENERGY_UNIT: > + scale = ENERGY_UNIT_SCALE; > + units = sp->energy_unit; > + break; > + case TIME_UNIT: > + units = sp->time_unit; > + break; > + default: > + return value; nit: maybe setting units and scale explicitly in each entry could be better for maintainability, but potayto/potahto > +static int spel_register_powercap(struct spel_system *sp) > +{ > + struct spel_domain *sd; > + struct powercap_zone *power_zone = NULL; > + int nr_pl, ret, i; > + > + /* Register SYS domain as parent zone */ > + for (sd = sp->domains; sd < sp->domains + SPEL_DOMAIN_MAX; sd++) { > + if (sd->id == SPEL_DOMAIN_SYS) { > + nr_pl = spel_find_nr_power_limit(sd); > + > + power_zone = powercap_register_zone(&sd->power_zone, > + sp->control_type, sd->name, > + NULL, &zone_ops, nr_pl, > + &constraint_ops); > + if (IS_ERR(power_zone)) { > + dev_err(sp->dev, "Failed to register power zone %s\n", > + sd->name); > + return PTR_ERR(power_zone); > + } > + sp->power_zone = power_zone; > + break; > + } > + } > + > + if (!power_zone) { I believe this is only possible if ARRAY_SIZE(sp->domains) == 0, but it's not obivous that it's to protect it from that specifically [...] > + /* Map spel domain registers (energy counters) */ > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nodes"); > + if (!res) { > + dev_err(dev, "Failed to get nodes resource\n"); > + return -EINVAL; > + } > + sp->node_base = devm_ioremap_resource(dev, res); > + if (IS_ERR(sp->node_base)) > + return PTR_ERR(sp->node_base); devm_platform_get_and_ioremap_resource() [...] > +static void spel_remove(struct platform_device *pdev) > +{ > + struct spel_system *sp = platform_get_drvdata(pdev); > + int i; > + > + if (!sp) > + return; > + > + /* Unregister in reverse order: children first, then SOC, then SYS */ > + for (i = SPEL_DOMAIN_MAX - 1; i >= 0; i--) > + powercap_unregister_zone(sp->control_type, &sp->domains[i].power_zone); Could you try adding a devm_ variant of these register functions? [...] > +static const struct of_device_id spel_of_match[] = { > + { .compatible = "qcom,spel" }, The compatible must contain a SoC name Konrad